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Having successfully taped
out over 50 ASICs, following are some of the testimonials given to TTM
from some of our customers:
"Canesta very warmly recommends TTM for
back-end chip projects. We asked TTM to do the almost impossible by
assigning them the task of placing and routing a mixed signal and a
digital SOC chip with full verification. The work was completed in record
time. The response and professionalism of TTM is highly appreciated. We
have decided to have TTM at the top of our list for all our future back
end-chip projects."
Shiraz M. Shivji, VP Engineering,
Canesta.
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"Time-to-Market's dedication and expertise was critical to
the successful completion of our design. The ASIC is quite large and
complex, in excess of 60 million transistors, and yet first-pass
silicon was running mission code within 24 hours. This is almost
unheard of in the industry."
Peter J. Roman, VP
of Engineering and Founder, Netcontinuum,
Inc.
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"Due to the efficiency and knowledgeability of the TTM team,
plus their excellent back-end design methodologies, Paxonet
Communications were able to resolve DRC, LVS, IR Drop and Parasitic
extraction in a very timely manner. This was achieved by using TTM's state of the art design verification methodology in 0.13U
Process."
Dinesh Mahale, Director of Engineering,
Paxonet Communications.
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"TTM has been Imedia Semiconductor's Physical Design House
for the last 2 years and they have successfully taped out two
time-critical ICs for us. TTM enabled us to switch to COT with
reduced risk and minimal setup time, which led us to achieve
first time success with silicon."
Aiman
Kabakibo, VP of Engineering, Imedia
Semiconductor.
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