Tarek provides the following verification services Vera and e Languages Replacement Although Draco is language neutral, we recommend C/C++ for reusability and performance.
Virtual Silicon Co-Simulator (VSC) Virtual Silicon Co-simulation (VSC) enables system software and driver running on any existing test bench, not just test benches made of Draco components.
Design Interface Module (DIM) Tarek provides two types of DIMs, DIM-E represents the emulatable DIM (running on emulation environment) and DIM-V represents behavior DIM (Verilog or ESL C model).
Assertion Model Builder (AMB) The Best Assertion Tool The use of AMB as a reference model holder in the verification platform improves the efficiency of verification process.
Dynamic Simulation Control (DSC)
The dynamic simulation control (DSC) enables to maneuver and monitor the register, memory, and field values at run time.
Automatic Driver Generator (ADG)
Transform ASIC Internals into a Set of Properties in SDL
The SDL and RTL characterize the design and verification environment extensively in the form of object properties.
Predicate Random Test Generator (PRTG)
PRTG implements a super-layer of randomization that delegates power to create random sets of test cases in SDL. Such a specification is effective on both internal signals and external verification knobs.
Test Scenario Generation at the Electronic System Level
Test scenario is a reference set of input and output transaction sequences and associated tables that describe the relationships among the transactions.
System Description Language (SDL)
System Description Language (SDL) manages constraint random variables and data structures created by the random variables. It is designed to be automatically generated by tools, not engineers.
Draco Architecture
Draco models the real-world in the Electronic System Level (ESL) and bring it to the DUT.
We provides the following tools:
ASIM: Generating Sophisticated Scenarios at the Architecture Level
Support standard networking and multimedia protocols
By Any designer or verification engineer
API for non-standard protocols
PCI Express Compliance Suite
Hundreds of directed test cases and unlimited random test cases.
Includes all PCIE devices, such as root complex, end point, switch ports, and bridges
Functional Coverage Grader
An assertion checker based on the compliance check list published by PCIE-SIG.
Coverage merge from every test case
Extendible for coverage in the application
Predicate Random Test Generator (PRTG)
PRTG implements a super-layer of randomization that delegates power to create random sets of test cases. Such a specification is effective on both internal signals and external verification knobs. Internal signals including register bits and memory contents are set to the special value in resulting SDL test suites chosen from realistic vector space with equal or weighted probability.
Transaction Layer Verification Automation
Realistic multi-threaded TLP traffic generator for ease of transaction layer verification.
Data Link Layer Verification Automation
Plug&Play verification
Sophisticated DLCMSM state exerciser automatically and exhaustively performs endless statetransition looping.
Physical Layer Verification Automation
Plug&Play verification.
Sophisticated LTSSM state exerciser automatically and exhaustively performs endless statetransition looping.
Multi-Threaded Programming Interface
With the old PCI bus, a read or write bus cycle is atomic PCI Express is more complicated. A read may requires multiple completion packets to complete the read request., In reality, multiple reads from different threads may mixed together. This is especially true for devices that support
Fastest and Accurate PCIE Models
PCIE-VR has both cycle-accurate model (CAM) and transaction-level model (TLM).
Three kinds of APIs, i.e., C, Verilog, and DSC script for ease of programming.
Cycle-accurate Model (CAM) with PIPE, PCS, and serial interfaces.
Overview
PCIE-VR is a software implementation of the PCI Express (PCIE) standards. It is designed to be a Verification IP and an architecture model to facilitate ASIC designs with a PCIE interface. A set of verification automation tools and a compliance suite are added to increase the productivity.
