日本語
FinSimDeveloper
It is an interpretive event simulator of complete interchangeable Verilog-XL. In this version optional speed-up option such as compilation simulation etc. has been removed from Super-FinSim. Therefore, high accuracy can be simulated at a low price
Super-FinSim
Super-FinSim is a complete Verilog interchangeable simulator. All Verilog language specifications such as user definition primitiveness ( user Defined Primitive ), specify block, system task, system function, PLI 1.0, and VCF and SDF are supported.
Site license
The site license is also available. For more detail, please inquire Tamio Hoshino at hoshino@applistar.com.