Overview

Designed for High Performance Computing (HPC) applications, the DN_DPB_S327 is an FPGA-based peripheral that allows algorithm developers to employ hardware-in-the-loop acceleration utilizing a large grid of 27 cost effective, Altera Cyclone III FPGAs. Data movement to/from the FPGA grid is accomplished via 10/100 base-T Ethernet. We have several chassis configurations that can fit up to 20 of these cards in a single 19″ rack. Contact the factory for details.

The FPGAs: 27 Altera Cyclone III

The 3C120 from Altera’s Cyclone III family is utilized and this is the second largest member of this cost effective (read: CHEAP) family. The Cyclone III FPGA family has an impressive price/performance ratio for hardware-in-the-loop accelerators, with device power consumption much lower than the higher performance FPGA families.

Features of Cyclone III include an efficient, 4-input look-up table (LUT) logic, 9 Kb (2 x 9 Kb) block RAMs, along with 18 x 18 multipliers. We use the FF484 package, which gives us the highest possible circuit board density. 100% of the FPGA resources are dedicated to your application. The 27 FPGAs have the identical pinouts and can be configured with the same file, eliminating the time consuming task of optimizing the same design for 27 different pinouts. The FPGAs can be configured with different functionality and programmed separately.

FPGA configuration files can be stored on the board in a 64Gb NAND FLASH, but the most likely usage model is to have the host system store and orchestrate FPGA configuration.

We do not supply simulation, FPGA synthesis, or place/route. But expensive, third-party synthesis tools are not needed and no longer required to get good quality of results. In truth, the cost effective Quartus®II tools available directly from Altera have proven in benchmarks to be superior to the expensive third party tools.

An on board ARM9 processor

An AT91SAM9G20 AT91 ARM Thumb microcontroller runs an ARM9 processor at 400MHz. This processor boots to LINUX. Source and ‘C’ examples under a GPL license are provided. 100% of the processing power of this microcontroller is dedicated to your application. 64 megabytes (16M x 32) of external SDRAM is stuffed standard, along with a 64 Gb NAND FLASH. Processor code can reside in the NAND FLASH at boot, or downloaded via Ethernet. Data movement to/from the 27 Cyclone III FPGAs is aided by a Config FPGA (Cyclone II 3C16).

Debug

A JTAG connector provides an interface to SignalTap and other third party debug tools

Specs of FPGAs Available on the DNDPB_S327

Overview

Specs of FPGAs Available on the DNMEG_V6HXT

Overview

Extends 200-pin connectors 37 mm for clearing FPGA fans and other components. Recommended for DN6000K10, DN6000K10PCI(e), DN8000K10PCI-series.

Overview

The MP1000TX Gigabit Ethernet Daughter Board adds Gigabit Ethernet capabilities to the line of FPGA based emulation products available from the Dini Group (DN3000K10 series). The MP1000TX features the Intel LXT1000 Gigabit Ethernet transceiver for reliable full and half-duplex ethernet connectivity at speeds up to 1000Mbps with fallback support to 10 and 100 Mbps. The on-board Xilinx XC95144XL configures the LXT1000 at startup and synchronizes the transfer of data through the 200-pin Berg connector which mates to any of the DN3000K10(S) products. Any interface and configuration requirements to the FPGA are easily satisfied with the programmable Xilinx CPLD. The MP1000TX Daughter Board can be used with any of the supported FPGA based emulation products to develop and emulate network processing hardware, including high speed packet-processing at up to gigabit line rates.

Related Information

This daughter card is compatible with our line of DN3000K10 products:

• DN3000K10S
• DN3000K10

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Overview

The DN7002k10MEG is a complete logic emulation system that enables ASIC or IP designers to prototype system-on-a-chip (SOC) logic and memory designs for a fraction of the cost of existing solutions. The DN7002k10MEG is stand-alone or hosted via a USB interface. A single DN7002k10MEG configured with 2 Altera Stratix IV 4SE820s can emulate up to 13 million gates of logic as measured by LSI. This ASIC gate estimate does not include the embedded memories and multipliers resident in each FPGA. The DN7002k10MEG achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Altera’s Stratix IV FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGAs can be stuffed and each FPGA position can be stuffed with any available speed grade.

Stratix IV FPGAs from Altera

High I/O-count, 1760-pin, flip-chip BGA packages are utilized. The 4SE820 has a total of 1120 I/Os and the 4SE530 has 960 I/Os. Abundant interconnects are provided between FPGAs. All pins of all banks of each FPGA are utilized. Where appropriate, FPGA to FPGA busses are routed and tested unidirectional LVDS, run at 600MHz+ (1.2Gb/s) but can be used single-ended at a reduced speed (assume 225MHz). Example designs utilizing the integrated I/O block shift registers with DDR (double data rate) for pin multiplexing are included. A separate 72-pin main bus is connected to both FPGAs and an off-board connector. Thirty-six of these main bus signals are routed to the configuration FPGA. This product is backwards compatible with the Stratix III 3SL340. Each FPGA has a 30A VCCINT power supply.

Daughter cards

The DN7002k10MEG is easily adaptable to all applications via daughter cards. Six separate 400-pin FCI MEG-Array connectors allow for customization via expansion. Signals to/from these cards are routed differentially where appropriate and can run at the limit of the FPGA: 600MHz. Clocks, resets, and abundant (fused) power are included in each connector. Signals are routed from the FPGAs on a bank basis, and the daughter card selects the I/O voltage of the connector by driving the Vcc_I/O of the FPGA bank. The I/O voltage ranges are +1.5V to +3.3V. The DNMEG_Intercon card can be used to convert Daughter A2 and B2 to additional FPGA to FPGA interconnect.

Memory

A DDR2 SODIMM socket is connected to each FPGA. Each socket is tested to 350MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMMs (PC2-5300) work nicely and we can provide these for a small charge. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, RLDRAM I/II, SDR SDRAM, mictors, DDR1, DDR3, and others.

Easy Configuration via Compact Flash or USB

The configuration bit files for the FPGAs are copied onto a 128-megabyte Compact FLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Fully stuffed, the DN7002k10MEG configures in less than 10 seconds. Visibility into the configuration process is enhanced with an RS232 port. Multiple LEDs provide instant status and operational feedback.

Laboratory testing is showing that the amount of light provided by the LEDs is enough to function as traffic signals.

As always, reference material such as DDR2 SDRAM controllers, flash controllers, et al. is included (in Verilog, VHDL, C) at no additional cost.

Specs of FPGAs Available on the 7002k10MEG

Overview

The DNPCIe_10G_HXT_LL is a PCIe-based FPGA board designed to minimize input to output processing latency on 10Gb Ethernet packets. The primary application is for ultra low latency, high throughput trading without CPU intervention. Every possible variable that affects input to output latency has been analyzed and minimized. Raw 10 GbE Ethernet packets can be analyzed and acted upon without a MAC, interrupts, or an operating system adding delay to the process. This configurable hardware computing platform has the ability to achieve the theoretical minimum Ethernet packet processing latency.

The FPGA – Xilinx Virtex-6 HXT

We use a single FPGA from the HXT sub-family of Xilinx Virtex-6 in the FFG1923 package. This package supports 720 I/O with the majority utilized. Most are dedicated to a variety of off chip memory peripherals including QDR II+ for low-latency, high speed look-up, and DDR3 for performance oriented bulk storage. The HXT FPGAs contain high-speed transceiver PHYs of two different types. GTX transceivers are capable or handling data rates of 150 MB/s to 6.5 Gb/s, making these useful for lower speed Ethernet and GEN1/GEN2 PCI Express. The GTH transceivers are tuned higher, 2.488 to 11 GB/s, making them applicable to 10 gigabit Ethernet (10 GbE). Eight of the GTX transceivers are used for GEN2-capable PCIe. Four of the GTH transceivers are connected to 10 GbE SFP+ sockets. Another 8 GTX transceivers are connected to our standard GTX expansion connector, allowing for peripheral expansion but most applicable to in-chassis, board to board data daisy chaining.

Two possible FPGAs can be stuffed: HX380T or the HX565T. The HX380T comes in three speeds grades, with -3 being the fastest. The larger HX565T is limited to the -2 speed grade. This means the smaller device can be clocked at a higher frequency at the cost of slightly fewer FPGA logic resources. Table 1 depicts the resources of the two FPGAs with the Xilinx marketing exaggerations removed. These are both large FPGAs. The HX565T is capable of handling >4M ASIC gates of logic and is among the largest of the FPGAs shipping from any vendor in 2011. Features of the Virtex-6 HXT FPGAs include the efficient, dual-register 6-input look-up table (LUT) logic, 18 Kb (2 x 9 Kb) block RAMs, and second generation DSP48E1 slices (includes 25 x 18 multipliers). Floating point functions can be implemented using these DSP slices.

To give you an idea as to how large these FPGAs are, Xilinx has embedded processor IP called MicroBlaze. This processor is implemented in FPGA logic gates. Fifty (50!) or more of these MicroBlaze processors can be stuffed into an HXT565T with room to spare. Somewhat fewer if you incorporate IEEE 754 floating point.

Three Channels of 10 GbE

The HXT FPGAs have transceivers capable of 10 GbE. The physical interface is handled using SFP+ modules. This allows you to bypass a MAC if necessary and process raw Ethernet packets. The DNPCIe_10G_HXT_LL has 3, 10 GbE channels.

QDR II+ SSRAM

We use 4 individual quad data rate static RAMs (QDR II+ SSRAM) in the 2M x 36 configuration. This style of memory has separate input and output data paths, enabling maximum read/write data bandwidth with minimum latency. These four separate memories can be controlled individually, but any two (2M x 72), three (2M x 108), or four (2M x 144) of the QDRII+ SRAMs can be treated as a single memory. The maximum tested frequency of this memory is 400 MHz. To minimize processing latency, we suspect it will be best to clock these QDRII+ SRAMs at 312.50 MHz, exactly twice the internal Ethernet controller frequency of 156.25 MHz. The HXT FPGAs are capable of generating internal 2x clocks that are phase synchronous, eliminating the latencies associated with the tricky re-synchronization of data moving between different clock frequencies. The internal controller can be optimized in any way you choose. We, of course, provide several verilog examples for no charge that you are welcome to use. All functions of the QDR II+ SSRAM can be exploited, including concurrent read and write operations and four-tick bursts. The only real limitation is the amount of time and effort spent in customizing the individual memory controllers.

DDR3

A single DDR3 DIMM socket enables up to 4GB of memory for bulk storage and lookup. Assuming a 4GB DIMM, the memory configuration is 512M x 72. Assuming a -2 or -3 speed grade FPGA, this interface is tested at the maximum FPGA I/O frequency: 533 MHz (1066 Mb/s with DDR). You are welcome to use this memory as 64-bits with 8 bits of error correction (ECC), or as a 72-bit memory without correction.

To minimize data synchronization across clock boundaries, it probably makes sense to clock this DDR3 interface at a 3x multiple of the base Ethernet frequency of 156.25 MHz, which is 468.75 MHz. A 3x phase synchronous clock can be easily generated internal to the FPGA, allowing zero latency synchronous data transfers between the Ethernet packet receiving logic and the DDR3 memory controller. The DDR3 controller can be optimized in any way you choose. We, of course, provide several verilog examples for no charge that you are welcome to use. All functions of the DDR3 DRAM can be exploited and optimized. Up to 8 banks can be open at once. Timing variables such as CAS latency and precharge can be tailored to the minimum given your operating frequency and the timing specification of the exact DDR3 memory utilized. As with the QDRII+ SRAM, the only real limitation is the amount of time and effort spent customizing the DDR3 memory controller to your needs.

PCIe – Customizable 8-lane, GEN2 PCI Express

PCIe is connected directly to the FPGA via 8-lanes of GTX transceivers. The interface is fully GEN2 capable. We ship PCIe IP that is a full function, fixed, 8-lane master/target. To gain access to the PCIe interface, this IP must be integrated with your application. We can help configure this IP to your needs, including BAR sizes. Additionally we can optionally add or subtract DMA engines, scratchpad memories, interrupts, and other host-related functions to maximize the performance, while utilizing the minimum FPGA resources. Drivers for ‘C’ source for several operating systems are included no charge. Partial reconfiguration of the FPGA is supported via the PCIe interface.

Board to Board Daisy Chaining and Expansion

These boards can be stacked in a PCIe system utilizing the GTX Expansion Header. We connect 8-lanes of the GTX transceivers to a high speed connector. This enables high board to board communication at the rate of 10 GB/s.

How Everything Works …

With direct data feeds such as NASDAQ ITCH and OUCH, the DNPCIe_10G_HXT_LL contains all of the basic functions required to minimize the amount of time it takes to receive Ethernet packets, process them, and respond deterministically. The MAC, operating system et al, can be bypassed. There are no interrupts. No operating system. Not a single clock cycle is wasted here, enabling a near theoretical minimum in-to-out response time. For algorithms requiring processing, FPGA resources can be hard coded to perform the task. This includes real-time Monte Carlo analysis and floating point.

Specs of FPGAs Available on the DNPCIe_10G_HXT_LL

Overview

The LVDS/Camera Link Interface supports 5 input channels of Camera Link and 6 output channels as defined by the Camera Link specification (October 2000). High performance LVDS interface chips from National Semiconductor are used on the interface making for robust, high-speed connections. The Camera Link MDR26 cables are mounted directly to the circuit board. If Camera Link is not required, a custom cable package is available that allows the construction of custom cables. This allows the use of any or all of the LVDS interfaces for other purposes. A Xilinx VirtexII-Pro FPGA is used as an interface chip and 100% of the FPGAs resources are available for user application. Data is transferred through the FPGA to the ASIC Emulation host through a standard 200-pin connector and/or through 8 separate, bi-directional RocketI/O (MGT) channels. A video input channel, based on the NXP SAA7113H, is used to digitize a composite video signal.

This product is intended to be a peripheral to any of The DINI Groups ASIC emulation products, but can be used stand-alone.

Overview

The DNBFC_S12_12_Cluster is a complete, 4U rack mount FPGA acceleration cluster. The standard configuration contains the following

This system contains the maximum number of cost effective FPGA that can be reasonability integrated into a 4U chassis. Power and cooling are the constraining variables. High performance data paths between FPGA boards enable data movement under algorithmic control that is wholly separate from the host processor, enabling FPGA-based acceleration of whole new classes of data intensive algorithms.

In short, the DNBFC_S12_12_Cluster is a massive number of large, low cost FPGAs integrated with an excellent dual Xeon-based processor host. High speed serial cables between FPGA cards add as much a 5 GB/s data throughput within the chassis.

A partial list of possible applications includes:

• bioinformatics
• Genomic search
• financial analytics
  • low latency analysis
  • derivative calculations
• image processing
• signal processing
• radar
• scientific computing
• video compression
• encryption/decryption (cryptography )

The Processor Card – dual Xeons

Central to the DNBFC_S12_12_Cluster is the Trenton JXT6966 host processor card. This single-board computer has dual Intel Xeon processors, clocked at 2GHz. Each processor has 3 SODIMM slots and we stuff 2GB DDR3 memories into each, resulting in 6GB of memory per processor. The processor card has two 10/100/1000 Base-T Ethernet ports, along with 4, USB2.0 ports. The chassis can host up to 2 SATA drives. Power and cooling are provided for up to 12 DNBFC_S12_PCIe cards. Power is cabled to the FPGA cards separately and not drawn from the motherboard, allowing us to exceed the 25W slot PCIe limitation. The power budget is 50W per board. Note that this requires a lot of airflow and the fans are noisy. Fully populated, the system is perhaps too noisy to be in close quarters with an engineer.

The DNBFC_S12_PCIe – 13 Xilinx Spartan-6 FPGAs

Designed for high performance computing (HPC) applications, the DNBFC_S12_PCIe is an FPGA-based peripheral that allows algorithm developers to employ hardware-in-the-loop acceleration utilizing cost effective, Xilinx Spartan-6 FPGAs. The DNBFC_S12_12_Cluster can host up to 12 of these FPGA cards. Data movement between the host processor and each FPGA card is accomplished via a fixed 4-lane, GEN1 PCIe interface. Each Spartan-6 FPGA has its own 128M x 16 DDR3 memory capable of clocked speeds up to 400MHz (800 Mb/s per data pin). Two additional 128M x 16 DDR3 memories are connected to the USER Dataflow Manager FPGA (LX150T) for bulk data storage.

The DNBFC_S12_PCIe contains a fixed, full function, 4-lane master/target PCIe controller, freeing the user from integrating the PCIe function in with the application code.GEN1 PCIe is utilized here.

Spartan-6 FPGAs from Xilinx

The Xilinx LX150 (and LX150T) Spartan-6, 45 nm FPGA is utilized and it is the largest member of this cost effective (read: CHEAP) family. The Spartan-6 FPGA family has an impressive price/performance ratio for hardware-in-the-loop accelerators, with device power consumption much lower than the higher performance FPGA families.

Features of Spartan-6 include efficient, dual-register 6-input look-up table (LUT) logic, 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices (includes 18 x 18 multipliers), and DDR3 memory controllers. Enhanced IP security with AES and Device DNA protection is new to this family and helps keep your proprietary IP secret.

We use the largest device from this family, the LX150, in the FF484 package. 100% of the 13 FPGAs on each board are dedicated to your application. All FPGAs, excluding the PCIe controller, are configured from the host via PCIe. The PCIe FPGA can be updated remotely in the field.

Memory

Each of the 12 FPGAs has a dedicated 2Gb DDR3 memory. We test the FPGA to memory interface at the fastest frequency allowed by the given speed grade of FPGA stuffed. The fastest speed grade is -3 and if stuffed with the LX150-3, we test this interface at 400MHz. DDR3 is double data rate, multiplying to 800 Mb/s per pin. The configuration is 128M x 16, yielding 12.8 Gb/s (1.25 GB/s) maximum data rate per DDR3 memory.

The Xilinx Spartan-6 family has integrated hard IP for controlling this dedicated DDR3. The fixed memory controller block (MCB) significantly eases the implementation of high performance dataflow. The MCB can have up to 6 ports, and each port can be configured to have a 32-bit, 64-bit, or 128-bit bus interface. Configurable arbitration is included and up to 8 memory banks can be open simultaneously.

The User FPGA Dataflow Manager has two of its own 128M x 16 DDR3 memories and these memories are useful for bulk memory storage.

As always, we provide examples and references designs to help you with all of your memory interface issues. Please check with us to make sure that what we ship for no charge meets your requirements.

Board to Board Dataflow via GTP serial transceivers

The DNBFC_S12_PCIe has expansion capabilities using the gigabit transceivers on the LX150T, labeled on the block diagram as the USER DATAFLOW MANAGER FPGA. The LX150T has a total of eight, 3.125 Gb/s transceivers. Two, non-proprietary Samtec connectors contain 4 GTP lanes each. Eight, general purpose FPGA I/Os are also included. A standard cable is used to connect the installed boards in a daisy chain. The last board in the chain is connected back to the first board completing the loop. Four GTP lanes clocked at 3.125 GHz are capable of transmitting and receiving a data bandwidth of more than 2 GB/s (>1GB/s each for independent TX and RX). This GTP daisy chain allows the user to move large amounts of data board to board without the intervention of the host processor, significantly speeding up algorithms that contain multiple different stages.

Power Consumption

The PCI Express specification limits slot power to 25 watts. The DNBFC_S12_PCIe is capable of consuming power significantly beyond that. In addition to the PCIe fingers, a separate HDD connector adds a second path for power. This product is shipped with adequate heatsinking to consume 50 watts/board, and we supply enough
airflow to dissipate the heat for 12 installed DNBFC_S12_PCIe. We ship high reliability passive heatsinks on the FPGAs with an option for active heatsinks (i.e. with fan).

Status LEDs, Debug

Although no specific testing was performed, sophisticated statistical finite element models and back of the envelope calculations are showing the number of status LEDs to be bright enough to provide emergency illumination for a small parking structure. These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition to emergency lighting. A JTAG connector provides an interface to ChipScope and other third party debug tools.

List of available FPGAs for DNBFC_S12_10_Cluster