Products -Fintronic USA, Inc-
Fintronic USA, Inc.
Efficient Verilog simulator Super-FinSim.
Conforming the IEEE standard . PLI,SDF,VCD Support.
We are offering popular edition Verilog simulator FinSimDeveloper
with special price!
The number of elements is unrestricted. IEEE standard conforming. PLI, SDF, and VCD support.
Fintronic USA, Inc
About Fintronic USA
The Fintronic USA Inc.is a vender offering an efficient CAD tool for the electronic equipment industry. The EDA(Electronic Design Automation) is a necessary and essential tool for design of the digital circuitry. The first step in designing the digital circuitry is describe essential functions for the circuit accurately. This can be done easily by using the hardware design description languages. Among those languages,Verilog HDL and VHDL currently are two popular languages . The design description verifies whether designer executes real operations by simulating it follows with the digital circuit simulator or not. If the verification of the operation level is passed, these descriptions are made in more detailed and concretized from the description of the register transfer level to the gate level.
Recently, it is also possible to create the description of the gate level automatically by using the logic synthesis tool. These descriptions also add delay information that related to arrangement and the wiring result, and confirm whether operate timing do not encounter any problems or not. The final confirmed circuit information will be sent to manufacturing facility. But till that time, simulation is executed many times. In the electronic equipment industry recently, it is necessary for simulator to be faster due to the demand of complicated circuit market. The reason for that is if faster simulator is used, the design cycle can be shortened for several months. Fintronic USA is providing the world market with products that are one step ahead even in CAD world by using the most advanced techniques. Enhanced Cycle Simulation Technology is one of the results recently developed by Fintronic USA. Thank to this technique, the speed of the simulation for uniform design file can be ten times faster. This technology was applied into the latest Super FinSim product of Fintronic. It is the first simulator that supports the mixture simulation of event simulation and cycle simulation.
Beside Verilog simulator, Fintronic USA also offers EDA tools which include FinCov code coverage analysis tool. By using those tools, designers can get feedback related to the quality of the test vector after the digital circuitry is evaluated. Nevertheless, FinVA not only can compile the description of Verilog as a very useful tool for CAD designer but also can convert into intermediate code. It becomes easy for this intermediate code to develop analysis tools/synthesis tool/validator of Verilog by using along with the FinVFI package.
Super-FinSim of Fintronic is a simulator that boasts of the best performance in a complete Verilog interchangeable simulator. Super-FinSim offers PLI1.0, SDF, and VCD, and can create an environments integrated on the workstation which uses the source level debugger and the simulation wave type display tool etc. from the third party.
Fintronic extends Enhanced Cycle Simulation and introduces novel code coverage tool
Menlo Park, CA (May 21, 1996) Fintronic USA, Inc. which recently introduced the innovative Enhanced Cycle Simulation Technology (ECST) to its line of EDA products, announces today that it has successfully extended this ground-breaking technology to a wider class of Verilog designs for which the cycle simulation paradigm could not be used before. FinSim-ECS which supports the entire Verilog HDL consists of FinSim, a full fledged Verilog simulator and the ECS engine. FinSim-ECS automatically identifies the parts of the circuit that are suitable for simulation on the ECS engine and the rest is simulated by FinSim. Fintronic has improved the ECS engine so that modules with full timing specifications as well as some RTL-level modules can be now simulated by the ECS kernel without any change in the original Verilog code. Fintronic has specifically made a point out of testing its new technology on designs known in the industry for some time, such as the CMU and the DA Solutions benchmarks, in order to prove that this technology does not require a new design methodology.
02/26/96 1600 Fintronic uses Enhanced Cycle Simulation
Menlo Park, CA (Feb. 26, 1996) Fintronic USA, Inc. the supplier of high performance hardware description language driven simulators announces today that it has introduced enhanced cycle simulation technology (ECST) to its FinSim verilog simulator, in addition to its already existing event-driven, compiled and interpreted technologies.
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