Products

DN9000K10

  • USB2.0-hosted logic prototyping system with 2-16 Xilinx Virtex-5 FPGAs
    • 16 LX330s (FF1760)
    • 100% FPGA resources available for user application
  • 32M+ ASIC gates (LSI measure) with 16 LX330s
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 450 MHz differential chip-to-chip DDR (900Mb/s)
  • Reference designs for integrated I/O pad ISERDES/OSERDES
    • 10x FPGA to FPGA pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
    • Main Busses for global connectivity:
      • Main Bus Horizontal (MBH), all FPGAs: 80 single-ended signals
      • Main Bus Vertical (MBV), right two columns of FPGAs: 80 single-ended signals
    • Hooks for other third-party partitioning solutions
  • 6 separate DDR2 SODIMMs (250MHz)
    • 64-bit data width, 250MHz operation
    • PC2-5300
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available:
      • QDR SSRAM, Mictor, RLDRAM, SSRAM, DDR3, DDR1, interconnect, SDRAM DRAM, FLASH and others
  • 4 board-level global clock networks (GCLK0, GCLK1, GCLK2, REFCLK)
    • Separate programmable synthesizers for each network
    • User-configurable via Compact FLASH or USB
    • Separate global reference clock network for IDELAY chain delay resolution (REFCLK)
    • Global clocks networks distributed differentially and balanced
    • Single-step clocking available on each global clock network
    • 3 external differential clock inputs can be multiplexed in to global clock networks (via SMAs)
  • 8, 400-pin MEG-Array connectors (FCI)
    • 96 LVDS pairs + clocks (or 192 single-ended)
    • 450MHz on all signals with LVDS
    • Reset, presence detect
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)
  • Fast and Painless FPGA configuration
    • Compact FLASH, and/or USB
    • Integrated sanity checks on configuration files
    • Accelerated configuration readback
  • 4 separate parallel readback busses
  • Custom base plate (standard) and optional rackmount chassis
    • Provides protection from those drooling engineers
  • 4, RS232 ports for MicroBlaze or embedded uP debug
    • Accessible from all FPGAs via Configuration FPGA
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro and other third party tools
  • Convert a pair of MEG-Array expansion connectors to interconnect with the DNMEG_Intercon.
    • Add 186 single-ended OR 93 pairs LVDS:
      • (FPGA 8 to 12)
      • (FPGA 3 to 7) AND/OR (FPGA 11 to 15)
  • Enough status LEDs to perform a cosmetic peel on the face of a walrus