DNVUF4A
Godzilla’s Butcher on Steroids (GBS)
ASIC Prototyping Engine Featuring Xilinx Quad Virtex UltraScale FPGAs

- Four Xilinx Virtex UltraScale FPGAs (A2892):
- VU440-3, -2, -1 (fastest to slowest)
- 116+ million ASIC gates (ASIC measure)
- Hosted via
- 4-lane GEN3 PCIe via iPASS cable, USB2.0
- 10/100/1000BASE-T Ethernet, or stand alone
- Memory can be added using DINAR1_SODM204 on a DINAR1 expansion connector:
- High Speed interfaces on each FPGA:
- QSFP+ module for 4x 10 GbE or single 40 GbE
- 4 SFP+ modules
- DNTC (DINI Transceiver Connector), 16-lanes each. One per FPGA. Each capable of supporting:
- 16-lane PCIe (GEN1/GEN2/GEN3)
- 2x CX4 – Ethernet, XAUI, Infiniband
- 16x SFP+ modules for 10 GbE
- 4x QSFP+ modules for 40 GbE
- 16x USB3.0/2.0 (A,AB,B)
- 16x Serial ATA II (SATA II)
- 16x SMA
- TMB busses – Preconfigured high speed data movement between field FPGAs and Config FPGA
- 5 GB/s DMA between FPGAs and Config FPGA
- A↔B, A↔C, A↔D, B↔C, B↔D,C↔D
- FPGA[A,B,C,D] ↔ Config FPGA (Marvell uP)
- Main Bus (YMB) for bussed interconnect between all four FPGAs
- Marvel MV78200 Discovery Innovation Dual CPU (socketed)
- 1 GHz clock
- Dual USB2.0 ports (Type B connector)
- Dual Serial-ATA II connectors for 2 external hard drives (SATA II)
- Gigabit Ethernet interface
- 10/100/1000 GbE (RJ45 connector)
- SheevaTM CPU Core (ARM v5TE compliant)
- Out-of-order execution
- Single and double-precision IEEE compliant floating point
- 16-bit Thumb instruction set increases code density
- DSP instructions boosts performance for signal processing applications
- MMU to support virtual memory features
- Dual Cache: 32 KB for data and instruction, parity protected
- L2 cache: 512 KB unified L2 cache per CPU (total of 1MB), ECC protected.
- 1 GB external DDR2 SDRAM
- Organized in a 128M x 64 configuration
- 400 MHz (800 MHz data rate with DDR)
- RS232 port for terminal-style observation
- After configuration, both CPUs dedicated entirely to user application
- Linux operating system
- Source and examples provided via GPL license (no charge)
- ˜15 seconds to CPU boot
- Five independent low-skew global clock networks and single fixed clock
- Five, high-resolution, user-programmable synthesizers for G0-G4
- Silicon Labs Si5326: 2kHz to 945 MHz
- User configurable via Marvell uP RS232, USB, PCIe, or Ethernet
- Global clocks networks distributed differentially and balanced
- Flexible customization and stacking via 12 daughter card connectors per FPGA
- DNBC (DINI Bank Connector) expansion connector
- One bank per connector
- Daughters cards (1 to 12 connectors )
- Added FPGA to FPGA interconnect (inter or intra board)
- Connector: non-proprietary; readily available; cheap
- 24 LVDS pairs + 4 single-ended, + clocks
- TBD (800MHz?) on all signals with source synchronous LVDS
- Signal voltage set by daughter card (+1.2V to +1.8V)
- Reset
- Supplied power rails (fused):
- +12V (24W max), +3.3V (10W max)
- Pin multiplexing to/from daughter cards using LVDS (up to 10x)
- Noninvasive debug via FPGA register readback: DN_Readbacker
- Models for Mentor Flexras partitioning tool
- Fast and Painless FPGA configuration
- USB, cabled PCIe, Ethernet, JTAG
- Stand-alone configuration with USB stick
- Configuration Error reporting
- Accelerated configuration readback for advanced debug
- RS232 port for embedded FPGA-based SOC uP debug
- Accessible from all FPGAs via separate 2-signal bus
- Full support for embedded logic analyzers via JTAG interface
- Vivado Logic Analyzer and other third party solutions
- ProtoLinkTM debug connection to any/all FPGAs with DNBC adapter card: DNBC_ProtoLink
- Status FPGA-controlled LEDs:
- Enough multicolored LED’s to melt cheese.