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High Speed Serial I/O Daughter Card
Featuring Xilinx Virtex-6 HXT

  • ASIC prototyping daughter card, stand-alone, or PCIe-hosted Serial I/O
    • 10GbE/40GbE/100GbE
  • Xilinx Virtex-6 HXT FPGA (FF1923)
    • HX565T-2,-1 or HX380T-3,-2,-1 (fastest to slowest)
      • 24 GTH transceivers (to ~11 Gb/s)
      • 40 GTX transceivers (to 6.5 Gb/s)
      • Virtex-6 HX565T resources:
        • 2M ASIC gates (ASIC measure)
        • 354k flip-flop/6-input LUTs (708k total FFs)
        • 4MB embedded memory (1824, 18 kbit blocks)
        • 864, 25x18 multipliers
  • Multiple High speed serial I/O Interfaces:
    • CFP Module - 10 lanes (GTH):
      • Single 40GbE (IEEE 802.3bg) or 100GbE
        • IEEE 802.3ba and IEEE 802.3bg
        • CAUI, XLAUI, OTL4.10, OTL3.4, and STL256.4 et al.
      • 2 - QSFP+ Modules (GTH)
        • Single 40GbE or 4 channels of 10GBASE
      • 4 - SFP+ Modules (GTH)
        • 4 channels 10GbE
      • 8 - SFP+ Modules (GTX)
        • 8 channels 10/100/1000GbaseT
      • Dual Serial ATA II (SATA II) Host/Device
      • 8 channels on GTX Expansion header
      • 2 GTH channels on SMAs
  • Bulk memory: 240-pin DDR3 UDIMM
    • 72-bit data width (64-bit with 8-bit ECC)
    • 533MHz operation, PC3-8500
    • Addressing/power to support 16GB (+ ECC)
    • DDR3 Verilog/VHDL reference design provided (no charge)
    • Optional RLDRAM DIMM instead of DDR3 for ultra low latency
  • Optional cabled PCIe GEN1/GEN2 hosting (with DNMEG_CBL_GEN2)
    • Dual 1-lane, Dual 4-lane or single 8-lane
    • (Optional) PCIe clock slow down IP
  • Flexible, abundant clock resources
    • 4 board-level clocks configurable clocks
      • Silicon Labs Si5338
      • 0.16 to 710MHz
    • Fixed 150MHz oscillator for SATA II
    • Fixed 100MHZ oscillator for PCIe
  • Mount to DINI products with 400-pin MEG-Array connectors
    • 93 LVDS pairs + clocks (or 186 single-ended)
    • 550MHz on all signals with source synchronous LVDS
      • slower when used single-ended
    • Reset, presence detect
    • Pin multiplexing to/from motherboard using ISERDES/OSERDES and LVDS (up to 10x)
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
  • FMC (Vita 57) interface for use with off-the-shelf I/O boards
    • A/D-D/A, CameraLink, DSP, and RF Transceivers
  • Fast and Painless FPGA configuration with integrated uC and EEPROM
  • Dual RS232 ports for embedded uP debug and monitoring
  • Battery socket for configuration bitfile encryption
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro, Veridae, and other third party solutions
  • Enough status LEDs to mystify a small trout


The DNMEG_V6HXT is a complete various network interfaces solution featuring high speed serial I/Os. The DNMEG_V6HXT can be used

  • stand-alone, without hosting (contact factory for chassis options if required)
  • hosted by 8-lane PCIe cable (GEN1/GEN2)
  • plugged into ASIC Prototyping boards from the DINI product line as an expansion peripheral

A single DNMEG_V6HXT configured with the Xilinx Virtex-6, HXT565T can emulate up to 4 million gates of logic as measured by a reasonable ASIC gate counting standard. This gate count estimate number does not include embedded memories and multipliers resident in each FPGA. One hundred percent (100%) of the Virtex-6 FPGA HXT resources is available to the user application, but the user’s application must include all necessary MACs and the PCIe Bridge. The DNMEG_V6HXT achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx's 40nm Virtex-6 HXT family.

Virtex-6 HXT FPGAs from Xilinx

We use a single FPGA from the HXT sub-family of Xilinx Virtex-6 in the FFG1923 package. This package supports 720 I/Os and all are utilized. The HXT FPGAs contain high-speed transceiver PHYs of two different types. GTX transceivers are capable of handling data rates of 150 MB/s to 6.5 Gb/s, making these useful for lower speed Ethernet, Serial ATA, and GEN1/GEN2 PCI Express. The GTH transceivers are tuned higher, 2.488 to 11 GB/s, making them applicable to 10 gigabit Ethernet (10 GbE). Two possible FPGAs can be stuffed: HX380T or the HX565T. The HX380T comes in three speeds grades, with -3 being the fastest. The larger HX565T is limited to the -2 speed grade. This means the smaller device can be clocked at a higher frequency at the cost of slightly fewer FPGA logic resources. Figure 1 depicts the resources of the two FPGAs. The wild exaggerations added by the Xilinx marketing department have been violently extracted; the morning calm of reality restored. These are both large FPGAs. The HX565T is capable of handling >4M ASIC gates of logic and is among the largest of the FPGAs shipping from any vendor in 2011. Features of the Virtex-6 HXT FPGAs include the efficient, dual-register 6-input look-up table (LUT) logic, 18 Kb (2 x 9 Kb) block RAMs and second generation DSP48E1 slices (includes 25 x 18 multipliers). Floating point functions can be implemented using these DSP slices.

Network Prototyping with FPGAs at the High End …

40GbE/100GbE with CFP Module
The DNMEG_V6HXT hosts a single C-form pluggable (CFP) module that is connected to 10-lanes of GTH transceivers. A variety of CFP MSA fiber optic transceiver modules (not supplied) are compatible to this connector and provide PHYS for 40Gb/s and 100Gb/s applications. The user is required to provide the MAC IP for the FPGA.

40GbE with QSFP+
The DNMEG_V6HXT has two QSFP+ connectors. Each QSFP+ is attached to 4-lanes of GTH transceivers. A variety of QSFP+ PHYS can be used here, creating a single lane of 40GbE, or 4-lanes of 10GbE. Again, the user is required to provide the MAC IP for the FPGA.

10GbE with SFP+
The DNMEG_V6HXT has four SFP+ connectors, each attached to single GTH lane. Again, a variety of SFP+ PHYS can be used here, with the most popular being 10GbE.

10/100/1000 BaseT with SFP+ Eight SFP+ connectors are attached to single GTX lane. A variety of SFP+ PHYS can be used here, with the most popular being 1000BaseT.

Two Serial-ATA Ports (SATA II)
The FPGA has dual SATA II (Serial ATA II) connectors attached to GTX. With SATA IP integrated into the FPGA logic, SATA cables connected can provide additional high-speed data paths to off board peripheral.

GTX Expansion Header
Eight lanes of GTX are connected to our standard GTX expansion header (purple thing in block diagram). Daughter cards such as the DNSEAM_SFP can be used here to add 8 SFP sockets, potentially adding 1x/2x/4x Fibre Channel, 10/100/1000GbE Ethernet, XAUI, SATA or Serial RapidI/O to the mix.

All or any subset of the above interfaces high speed serial interfaces can be used simultaneously. Two GTH channels are connected to SMAs.

DDR3 - A large amount of local, bulk memory

A single PC3-8500 DDR3 UDIMM socket enables up to 16GB (plus ECC) of memory for bulk storage and lookup. With a 16GB UDIMM memory stick, the configuration is 2048M x 72. Using a -2 or -3 speed grade FPGA, this interface is tested at the maximum FPGA I/O frequency: 533 MHz (1066 Mb/s with DDR). You are welcome to use this memory as 64-bits with 8 bits of error correction (ECC), or as a 72-bit memory without correction.

This is the same UDIMM interface used in our blockbuster DNPCIe_10G_HXT_LL product. To minimize data synchronization across clock boundaries, important for networking applications, it probably makes sense to clock this DDR3 interface at a 3x multiple of the base Ethernet frequency of 156.25 MHz, which is 468.75 MHz. A 3x phase synchronous clock can be easily generated internal to the FPGA, allowing zero latency synchronous data transfers between the Ethernet packet receiving logic and the DDR3 memory controller. The DDR3 controller can be optimized in any way you choose. We, of course, provide several verilog examples for no charge that you are welcome to use. All functions of the DDR3 DRAM can be exploited and optimized. Up to 8 banks can be open at once. Timing variables such as CAS latency and precharge can be tailored to the minimum given your operating frequency and the timing specification of the exact DDR3 memory utilized.

Alternate UDIMM memories are in development, including an RLDRAM and a QDRII+ option.

Daughter cards for customization and expansion: MEG-Array and FMC

Two 400-pin FCI MEG-Array connectors are attached to a single interface on the FPGA. One MEG-Array connector is on the top and one the bottom. The signals are shared. The bottom connector is used when this card is designated as a peripheral to our ASIC prototyping product. The top connector is used when this card is used stand-alone and application of one of our many DNMEG daughter cards is useful. This is a non-proprietary, industry standard connector and the mating connector is readily available. We can provide the mating connector to you at our cost if you’d like to customize your own daughter card. We are not fans of proprietary, hard-to-get, outrageously priced expansion connectors. The 192 signals (96 pairs) to/from each of these MEG-Array expansion connectors are routed differentially and can run at the limit of the Virtex-6 FPGA I/Os: 710 MHz. Clocks, resets, and presence detection, along with abundant (fused) power are included in each connector.

FMC (Vita-57)
FPGA Mezzanine Card, or FMC, as defined in VITA 57, provides a specification describing an I/O mezzanine module with connection to an FPGA or other device with reconfigurable I/O capability. We»ve added an FMC interface to the DNMEG_V6HXT. Most vendors of FMC daughter cards tend to ignore the specification, making this interface standard a questionable option. Also, the total number of I/Os in the specification is much too small. But there are some good A/D and D/A cards that adhere enough to the specification to be useful.

Easy Configuration via PCIe, USB, or Ethernet

Configuration of the FPGAs is under the control of an embedded CPU, an ARM-based LXC174 from NXP. Xilinx is not nice enough to supply a serial PROM large enough to configure the HXT565, so we need to use rather exotic methods to create enough onboard EEPROM storage for this function.

Status LEDs, Debug

As with all of our ASIC emulation boards, the DNMEG_V6HXT is loaded with LEDs. The LEDs are stuffed in several different colors (red, green, blue, orange et al.). Blinking these LEDs in a controlled fashion can confuse a trout. While this is unlikely to be fatal to the little fish, make sure an adult is present and wear eye protection when testing this feature. These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition to the task of distracting fish. A JTAG connector provides an interface to ChipScope, Veridae, and other third party debug tools.

Specs of FPGAs Available on the DNMEG_V6HXT

Related Documents

Product Brief [HiRes - LoRes]

Product Block Diagram
Product Manual
How-To fan installation video

Related Resources