Overview

The DN7002k10MEG is a complete logic emulation system that enables ASIC or IP designers to prototype system-on-a-chip (SOC) logic and memory designs for a fraction of the cost of existing solutions. The DN7002k10MEG is stand-alone or hosted via a USB interface. A single DN7002k10MEG configured with 2 Altera Stratix IV 4SE820s can emulate up to 13 million gates of logic as measured by LSI. This ASIC gate estimate does not include the embedded memories and multipliers resident in each FPGA. The DN7002k10MEG achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Altera’s Stratix IV FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGAs can be stuffed and each FPGA position can be stuffed with any available speed grade.

Stratix IV FPGAs from Altera

High I/O-count, 1760-pin, flip-chip BGA packages are utilized. The 4SE820 has a total of 1120 I/Os and the 4SE530 has 960 I/Os. Abundant interconnects are provided between FPGAs. All pins of all banks of each FPGA are utilized. Where appropriate, FPGA to FPGA busses are routed and tested unidirectional LVDS, run at 600MHz+ (1.2Gb/s) but can be used single-ended at a reduced speed (assume 225MHz). Example designs utilizing the integrated I/O block shift registers with DDR (double data rate) for pin multiplexing are included. A separate 72-pin main bus is connected to both FPGAs and an off-board connector. Thirty-six of these main bus signals are routed to the configuration FPGA. This product is backwards compatible with the Stratix III 3SL340. Each FPGA has a 30A VCCINT power supply.

Daughter cards

The DN7002k10MEG is easily adaptable to all applications via daughter cards. Six separate 400-pin FCI MEG-Array connectors allow for customization via expansion. Signals to/from these cards are routed differentially where appropriate and can run at the limit of the FPGA: 600MHz. Clocks, resets, and abundant (fused) power are included in each connector. Signals are routed from the FPGAs on a bank basis, and the daughter card selects the I/O voltage of the connector by driving the Vcc_I/O of the FPGA bank. The I/O voltage ranges are +1.5V to +3.3V. The DNMEG_Intercon card can be used to convert Daughter A2 and B2 to additional FPGA to FPGA interconnect.

Memory

A DDR2 SODIMM socket is connected to each FPGA. Each socket is tested to 350MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMMs (PC2-5300) work nicely and we can provide these for a small charge. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, RLDRAM I/II, SDR SDRAM, mictors, DDR1, DDR3, and others.

Easy Configuration via Compact Flash or USB

The configuration bit files for the FPGAs are copied onto a 128-megabyte Compact FLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Fully stuffed, the DN7002k10MEG configures in less than 10 seconds. Visibility into the configuration process is enhanced with an RS232 port. Multiple LEDs provide instant status and operational feedback.

Laboratory testing is showing that the amount of light provided by the LEDs is enough to function as traffic signals.

As always, reference material such as DDR2 SDRAM controllers, flash controllers, et al. is included (in Verilog, VHDL, C) at no additional cost.

Specs of FPGAs Available on the 7002k10MEG