Products

DN7002k10MEG

Altera Stratix IV
ASIC Prototyping Engine
13 Million ASIC Gates

  • USB 2.0-hosted logic prototyping system with 1-2 Altera Stratix IV FPGAs
    • Stratix-4 4SE530 or 4SE820 in high I/O package (FF1760)
      • - 30A VCCINT power per FPGA
    • Backwards compatible with Stratix III, 3SL340
    • 100% FPGA resources available for user application
  • 13M+ ASIC gates (LSI measure) with two Stratix IV 4SE820
    • 8M+ ASIC gates with two Stratix IV 4SE530
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 600MHz LVDS DDR chip-to-chip (1.2 Gb/s)
      • Characterized and tested
    • Reference designs for integrated I/O pad shift registers
      • 10x FPGA to FPGA pin multiplexing per LVDS pair
      • Greatly simplified logic partitioning
      • Source synchronous clocking for LVDS
  • 72-bit main busses for global connectivity
  • Auspy AES models for partitioning assistance
    • Hooks for other third-party partitioning solutions
  • 2 separate DDR2 SODIMMs (350MHz)
  • 3 low-skew global clock networks (GCLK[2:0])
    • Matched length and differentially distributed to each FPGA
    • Separate programmable synthesizers for each network (Si5326)
      • Ultra-low jitter (as low as 0.3 ps)
      • 2 kHz – 710 MHz
      • User configurable via Compact FLASH or USB
    • Alternate clock sources:
      • Configuration FPGA for generation of single-step or divided clock
      • SMA for external clock insertion
  • 4 Daughter Card global clock networks (DC_GCLK[3:0])
  • 6,400-pin MEG-Array connectors (FCI) for Daughter Card (DC) expansion
    • 1,116 total single-ended signals for daughter card expansion
      • 47/46 LVDS pairs (FPGA -> DC), 46/47 LVDS pairs (DC -> FPGA)
      • Can be used as 186 single-ended signals per connector
      • 600 MHz (1.2Gb/s)
      • Pin multiplexing to/from daughter cards using I/O shift registers (up to 10x)
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
  • Fast and painless FPGA configuration
    • Compact FLASH, USB and/or JTAG
    • Integrated sanity checks on configuration files
    • Accelerated configuration readback
  • RS232 port for embedded uP debug
    • Accessible from both FPGAs
  • Full support for embedded logic analyzers via JTAG interface
    • SignalTap and other third party tools
  • Convert a pair of MEG-Array expansion connectors to interconnect with the DNMEG_Intercon
  • Enough status LEDs to adequately direct traffic