ASIC Prototyping Engine
featuring Altera Stratix III
Hosted via 8-lane PCI Express



  • PCI Express (8-lane) logic prototyping system with 2-6 Altera Stratix III FPGAs
    • EP3SL340-4, -3, -2(slowest to fastest)
    • FF1760 package: 1,120 I/Os
  • Fixed 8-lane PCIe interface and controller provided
    • PCIe GEN1 rev 1.1 shipping now
    • PCIe GEN2 (with upgrade)
  • 15+ million ASIC gates (ASIC measure) when stuffed with 6 Stratix III 3SL340s
  • FPGA to FPGA interconnect is a mix of single-ended or LVDS
    • 600Mhz LVDS chip to chip (1.2 Gb/s)
    • LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
    • 10x pin multiplexer per LVDS par
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Main Bus(MB) connects all Stratix III FPGAs (96 signals)
    • Single-ended
  • Auspy models for partitioning assistance
  • 4 separate DDR2 SODIMMs (350MHz)
    • Direct connection to FPGAs A,C,F,D
    • 64-bit data width, 350MHz operation
    • PC2-4200 or better
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • FLASH
      • Mictor, USB PHY, Extra Interconnect
  • Seven independent low-skew global clock networks
    • G0, G1, G2, M48, EXT0, EXT1, REF
    • Three, high-resolution, user-programmable synthesizers for G0, G1, G2
    • User configurable via CompactFLASH, USB, and/or PCIe
    • All seven global clocks networks distributed differentially and balanced
      • Two independent single-step clocks
    • Seven independent external clocks inputs (single-ended or differential) can be injected onto low-skew global clock networks
  • Flexible customization via daughter cards
    • 3 daughter card locations: FPGAs D,E,F
    • 400-pin FCI MEG-Array connectors
    • 93 LVDS unidirectional pairs + clocks (or 186 single-ended)
    • 600MHz on all signals with source synchronous LVDS
    • Signal voltage set by daughter card (1.2v to 3.3V)
    • Reset
    • Supplied power rails (fused):
      • +12v (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using LVDS (up to 10x)
  • Fast and Painless FPGA configuration
    • CompactFLASH, USB, PCIe, JTAG
    • Configuration Error reporting
    • Accelerated configuration readback
  • RS232 port for embedded uP debug
    • Accessible from all FPGAs via separate 2-signal bus
  • Full support for embedded logic analyzers via JTAG interface
    • SignalTap, and other third-party debug solutions
  • 54 status FPGA-controller LEDs: enough illumination to decontaminate minimally processed vegetables


The DN7006k10PCIe-8T is a complete logic prototyping system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN7006k10PCIe-8T is hosted in an 8-lane PCIe bus (GEN1), but can be used stand-alone and configured via USB and/or CompactFlash.

A single DN7006k10PCIe-8T configured with 6 Altera Stratix III, 3SL340s can emulate up to 15 million gates of logic as measured by a reasonable ASIC gate counting standard and this number does not include embedded memories and multipliers resident in each FPGA. One hundred percent (100%) of the 3SL340s FPGA resources are available to the user application.

The DN7006k10PCIe-8T achieves high gate density and allows for fast target clock frequencies by utilizing the largest FPGA from Altera's Stratix III family. Any subset of FPGAs can be stuffed and we can accommodate any combination of speed grades.

Stratix III FPGAs from Altera

The DN7006k10PCIe-8T uses high I/O-count, 1760-pin, flip-chip BGA packages. The 3SL340 has 1,120 I/Os and all are utilized. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGAs. Where possible, FPGA to FPGA buses are routed and tested LVDS, run at 600MHz+ (which is 1.2 Gb/s if used in DDR mode).

Single-ended at the reduced speed of 225 MHz is characterized and tested. Example designs utilizing the integrated I/O shift registers with DDR for pin multiplexing are included. A 96-pin main bus (MB) is connected to all FPGAs including the configuration FPGA. The connection to the configuration FPGA allows for data movement via USB to any/all FPGAs.

Dedicated PCIe, 8-lane controller and exclusive IP for slowdown of PIPE interface

We ship the DN7006k10PCIe-8T with a full function, fixed, 8-lane master/target. Drivers and 'C' source for several operating systems are included at no cost. Easy PCIe core prototyping with our exclusive PCIe PIPE Slowdown Core

Specs of FPGAs Available on the DN7006k10PCIe-8T

Related Documents

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