ASIC Prototyping Engine
- PCIe hosted logic prototyping system available with Xilinx Virtex-4 FPGAs.
- Stuffing options for 1,2, or 3 FPGAs from the following list:
- 2 from ‘LX’ family FPGA A and FPGA B (FF1513):
- 1 from ‘FX’ family FPGA C (FF1152):
- Speed for FX MGT’s: (Delivery Estimate)
- 3.125Gbps – Now
- 6.25Gbps – Now
- 8.5Gbps – Never!
- 10.3Gbps – Never!
- 100% FPGA resources available for user application
- Nearly 3.7M ASIC gates (LSI measure)
- 2 from ‘LX’ family FPGA A and FPGA B (FF1513):
- All FPGA to FPGA interconnect LVDS differential
- 350Mhz differential chip to chip
- Reference designs for integrated ISERDES/OSERDES
- 10x pin multiplexing per LVDS pair
- FPGA A to FPGA B interconnect: >1800 signals
- Greatly simplified logic partitioning
- 5 separate programmable clock synthesizers (ICS8442)
- 3 Global clocks (ACLK, BCLK, DCLK)
- 2 for RocketI/O specific functions
- User configurable via SmartMedia, PCIe, or USB
- NXP PX1011A PCIe x1 PHY single-lane transceiver
- 2 — Transmit
- 2 — Receive
- 1 — Single PCI Access (SPCI)
- DMA Chaining/Scatter Gather
- Mailboxes, Interrupts
- Advanced FPGA configuration via PCIe, USB2.0 or SmartMedia
- Partial reconfiguration support on all FPGAs
- 2 separate DDR2 SODIMMs (200MHz)
- Connected to: FPGA B (LX), FPGA C (FX)
- 64-bit data width, 200MHz operation
- Addressing and power to support 4GB in each socket
- Verilog/VHDL reference design provided (no charge)
- DDR2 SODIMM data transfer rate: 25.6Gb/s
- Alternate pin compatible memory cards available (Click here to see the compatibility chart for DNSODM products):
- QDR SSRAM
- Gigabit serial I/O interfaces:
- 2 — 10G, Small form factor XFP (or SFP) modules
- SMA connectors for off-board cabling to 4 channels of rocketI/O
- Samtec cables for off-board cabling of 10 channels of rocketI/O
- Clocking options available for standard communications data rates for RocketIO:
- 1x, 2x, 4x Fibre Channel
- 10G Fibre Channel
- Serial Rapid IO Type 1,2,3
- Serial ATA Type 1,2
- PCI Express
- OIF SxI-5
- OIF SFI-4.2
- 1000 BaseX
- Ability to use embedded Ethernet MAC (FX) with SFP/XFP/SMA connectors.
- 8b/10b or 64b/66b encoding for all RocketIO channels
- Two PowerPC 405 Cores in FPGA C (FX)
- RS232 ports for PowerPC/uP observation/debug
- Multiplexed via SpartanII Configuration FPGA
- Configuration via SmartMedia/CompactFlash and USB
- Status LED’s
- Standalone operation with off-the-shelf ATX power supply.
- Two, 200-pin expansion connectors with 284+ connections
- Custom daughter cards
- DN3k10SD Observation Daughter Card
- DNPMC104 Embedded Systems Board Carrier
- Single-ended or LVDS, +2.5/3.3V tolerant
- We recommend using the Daughter Card Extender when using 200-pin daughtercards.
- Full support for embedded logic analyzers via JTAG interface
- ChipScope, ChipScope PRO
The DN8000K10PCIe-1 is a complete logic emulation system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions.
The DN8000K10PCIe-1 is hosted in a 1-lane PCI Express slot or can be used stand-alone. The user must supply the PCIe controller in FPGA A. The NXP PX1011A performs the PCI Express Phy function, freeing up all FX rocketI/Os for other applications.
A single DN8000K10PCIe-1 configured with 2 4VLX200s and a single 4VFX100 can emulate up to 3.7 million gates of logic as measured by LSI. And this number does not include the embedded memories and multipliers/ALUs resident in each FPGA. The DN8000K10PCIe-1 achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx’s Virtex-4 LX/FX families for logic and memory.
High I/O-count, 1513-pin, flip-chip BGA packages (for LX) and 1152-pin BGAs (for FX) are employed, providing for abundant, fixed interconnect between the FPGAs. All FPGA interconnect is single-ended or differential, with differential clocked at 350MHz+. In addition, the OSERDES/ISERDES functionality is thoroughly tested and characterized, allowing for 10x pin multiplying on differential pairs between FPGAs and dramatically easing the partitioning problem.
Two DDR2 SDRAM SODIMM sockets are provided, allowing for up to 8GB of DDR2 memory. Each socket is tested at 200MHz, and reference designs are provided. Alternate pin-compatible SODIMMs are available that contain FLASH, RLDRAM, SSRAM, QDR SSRAM, or Mictor connectors. A total of 304+ test pins are provided on the top of the PWB via two 200-pin expansion headers. These expansion headers can also be used for logic analyzer-based debugging or for pattern generator stimulus.
The DNPMC104 card can be mounted to any of these connectors, enabling an interface to A/Ds, D/As, and a host of other embedded system peripherals. Also, custom daughter cards can be mounted to these connectors as a means to interface the DN8000K10PCIe-1 to application-specific circuits. Two XFP modules can be used to support OC-192/STM-64, 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, and G.709 data streams and can be connected to routers, switches and network cards. Reference material such as DDR2 SDRAM controllers and PowerPC code is included (in Verilog, VHDL, C) at no additional cost.
Specs of FPGAs Available on the DN8000K10PCIe-1
- Product Brief
- Block Diagram
- User’s Manual
- Appendix – Clocks
- Appendix – Pin Summary
- MEG Array Daughter Card Interface Description
- Daughter Card Compatibility Guide
- QL5064_INTERFACE Module Description and Usage
- Mainbus Specification
- USB Specification
- SODIMM Connection Summary