‘Son of Monster
Virtex4 Based
ASIC Prototyping Engine

  • USB2.0-hosted logic prototyping system with 2 to 16 Xilinx Virtex-4 FPGAs
    • 14 ‘LX’ (FF1513):
      • 4VLX100-10,-11,-12
      • 4VLX160-10,-11,-12
      • 4VLX200-10,-11
    • 2 ‘FX’ family (FF1152):
      • 4VFX40-10,-11,-12
      • 4VFX60-10,-11,-12
      • 4VFX100-10,-11,-12
    • 100% FPGA resources available for user application
  • Nearly 23.7M ASIC gates (LSI measure) with 14 LX200s and 2 FX100s
  • FPGA to FPGA interconnect can be single-ended or LVDS
    • 350Mhz DDR chip-to-chip differential
    • 10x pin multiplexing using integrated SERDES modules (reference design provided)
      • - 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
    • Main Bus (MBUS) connects all LX FPGAs (80 +64 = 144 signals)
      • Single-ended
      • Reduced capacitance via quickswitches
      • 80 of these MBUS signals connected to FX FPGAs
    • 4 separate DDR2 SODIMMs (200MHz)
      • 1 DIMM each connected to LX FPGAs: 1,2,13,14
      • 64-bit data width, 200MHz operation
      • PC2-3200/PC2-4200
      • Addressing/power to support 4GB in each socket
      • DDR2 Verilog/VHDL reference design provided (no charge)
      • DDR2 SODIMM data transfer rate: 25.6Gb/s
      • Alternate pin compatible memory cards available (Click here to see the compatibility chart for DNSODM products):
        • QDR SSRAM
        • FLASH
        • SSRAM
        • Mictor
        • RLDRAM
  • Two PowerPC 405 Cores per FX FPGA (4 total with both FX FPGAs stuffed)
    • Embedded 350 MHz Harvard Architecture
    • Hardware Multiply/Divide Unit
    • Thirty-Two 32-bit General Purpose Registers
    • 16 KB 2-Way Set-Assoc. Instruction Cache
    • 16 KB 2-Way Set-Associative Data Cache
    • Memory Management Unit (MMU)
    • Timer Facilities
  • 3 board-level global clock networks (GCLK0, GCLK1, GCLK2)
    • Separate programmable synthesizers for each network
      • User configurable via SmartMedia or USB
    • Separate global reference clock network for IDELAY chain delay resolution (REFCLK)
    • Global clocks networks distributed differentially and balanced
    • Single-step clocking available on each global clock network
    • 3 external differential clock inputs can be multiplexed in to global clock networks (via SMAs)
    • 4 independent clock sources for each FX chip
      • 2 fixed low-jitter oscillators
      • 2 programmable synthesizers
    • Gigabit serial I/O interfaces:
      • Two 10Gbs small form factor XFP modules per FX FPGA (4 total)
        • 10.3 Gb/s (when available from Xilinx)
      • Two Small form factor SFP modules per FX FPGA (4 total)
      • -SMA connectors for off-board cabling to 4 channels of rocketI/O per FX FPGA (8 total)
        • 10.3 Gb/s (when available from Xilinx)
      • Samtec cables for off-board cabling of 8 channels of RocketIO per FX FPGA (16 total)
      • Clocking options available for standard communications data rates for RocketIO:
        • 1x, 2x, 4x Fibre Channel
        • 10G Fibre Channel, XAUI
        • Serial Rapid IO Type 1,2,3, Serial ATA Type 1,2
        • PCI Express, Infiniband
        • OIF SxI-5, OIF SFI-4.2
        • OC-48, 1000BaseX, OC-12
        • Aurora
      • Ability to use embedded Ethernet MAC with SFP and XFP modules (FX FPGA)
  • Flexible customization via daughter cards
    • 4, 400-pin Meg-Array connectors (FCI)
      • FPGAs 3,7,11,15
      • 93 LVDS pairs + clocks (or 186 single-ended)
    • 4, 300-pin Meg-Array connectors (FCI)
      • FPGAs 3,4,8,15
      • 62 LVDS pairs + clocks (or 124 single-ended)
    • 350MHz on all signals with LVDS
    • Signal voltage set by daughter card
    • Reset, presence detect
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)
  • Fast and Painless FPGA configuration
    • SmartMedia, Compact FLASH, and/or USB
    • Integrated sanity checks on configuration files
    • Accelerated configuration readback
      • 4 separate parallel readback busses
  • Custom base plate (standard) and optional enclosed chassis
    • Protection from those drooling engineers
  • 4, RS232 ports for PowerPC or embedded uP debug
    • Accessible from all FPGAs via Config FPGA
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro
  • Enough status LEDs to blind an OX
  • MEG Array Observation Daughtercard Available
  • Convert MEG Array expansion connectors to interconnect with the DNMEG_Intercon. Add 186 single-ended OR 93 pairs LVDS:
    • (FPGA 3 to 7) AND/OR (FPGA 11 to 15)
    • (FPGA 7 to 11)


The DN8000k10 is a complete logic emulation system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN8000k10 is stand-alone or hosted via a USB interface.

A single DN8000k10 configured with 14 Xilinx Virtex-4, XC4VLX200s and 2 XC4VFX100s can emulate up to 24 million gates of logic as measured by LSI. This number does not include the embedded memories and multipliers resident in each FPGA.

The DN8000k10 achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx's Virtex-4 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGAs can be stuffed.

Virtex-4 FPGAs from Xilinx

High I/O-count, 1513-pin, flip-chip BGA packages for the LX chips and 1152-pin flip-chip BGAs for the FX chips are utilized. Abundant fixed interconnects are provided between the FPGAs. All pins of all banks of each FPGA are utilized.

FPGA to FPGA busses are routed and tested LVDS, run at 350MHz+ but can be used single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A 144-pin main bus (MBUS) is connected to all FPGAs, excepting the FX FPGAs, which have connectivity to 80 of these main bus signals.

Daughter cards

Nine separate 300/400-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from these cards are routed differentially, and can run at the limit of the FPGA: 350MHz. Clocks, resets, and presence detection, along with abundant power are included in each connector.


Four separate DDR2 SODIMM sockets are connected to FPGAs 1, 2, 13, 14. Each socket is tested to 200MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMMs (PC2-3200/PC2-4200) work nicely and we can provide these for a small charge.

We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, and others.

High Speed Serial I/O Interfaces

Two FX-series chips are placed in positions 0 and 12 and can be stuffed with FX60s or FX100s. The rocketI/Os from each chip are attached to the following high-speed serial interfaces:

  • 2 SFP sockets (1 MGT each)
  • 2 XFP sockets (1 MGT each)
  • 4 separate TX/RX via SMAs (4MGTs)
  • 2 Samtec connectors for board-to-board cabling (4 MGTs each)

Easy Configuration Via SmartMedia/Compact FLASH/USB

The configuration bit files for the FPGAs are copied onto a 128-megabyte SmartMedia or Compact FLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process.

FPGA configuration can also be controlled via the USB interface. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process.

FPGA configuration occurs at the fastest possible SelectMap frequency - 48MHz. Multiple LEDs provide instant status and operational feedback.

As always, reference material such as DDR SDRAM controllers, flash controllers, and PowerPC code is included (in Verilog, VHDL, C) at no additional cost.

Specs of FPGAs Available on the DN8000K10

Chassis Pictures

Related Documents

Related Resources