Godzilla’s Part time Nanny
ASIC Prototyping Engine Featuring Xilinx Virtex-6
Hosted via 4-lane PCI Express (GEN1)

  • Hosted via
    • 4-lane GEN1 PCIe (v1.1) slot
    • USB2.0
    • 10/100/1000BASE-T Ethernet
    • Stand alone
  • 2 Xilinx Virtex-6 FPGAs (FF1760) from the following list:
    • LX760-2,-1,-1L
    • LX550T-2,-1,-1L (fastest to slowest)
    • 50A VCCINT power per FPGA
  • 11+ million ASIC gates (ASIC measure) when stuffed with 2 Virtex-6 LX760s
  • FPGA to FPGA interconnect is LVDS and GTX RocketI/O
    • 1.3 Gb/s when using DDR with -2 speed grade
      • 1.0 Gb/s with -1 speed grade
    • LVDS pairs are length balanced and tested!
    • LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
    • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Bus connecting Config FPGA with each field FPGA
    • 40 signals, single-ended (NMB[A:B])
  • RocketIO GTX Transceivers (Configuration FPGA)
    • PCI Express Cable (x4)
    • SATA - Host (x1)
    • SATA - Device (x1)
    • SFP (x1)
  • Auspy board interconnect models for logic partitioning assistance
  • Marvel MV78200 Discovery Innovation Dual CPU
    • 1 GHz clock
    • Dual USB2.0 ports (Type B connector)
    • Dual Serial-ATA II connectors (SATA II)
    • Gigabit Ethernet interface
      • 10/100/1000 GbE (RJ45 connector)
    • SheevaTM CPU Core (ARM v5TE compliant)
      • Out-of-order execution
      • Single and double-precision IEEE compliant floating point
      • 16-bit Thumb instruction set increases code density
      • DSP instructions boosts performance for signal processing applications
      • MMU to support virtual memory features
      • Dual Cache: 32 KB for data and instruction, parity protected
      • L2 cache: 512 KB unified L2 cache per CPU (total of 1MB), ECC protected.
    • 1 GB external DDR2 SDRAM
      • Organized in a 128M x 64 configuration
      • 400 MHz (800 MHz data rate with DDR)
    • RS232 port for terminal-style observation
    • After configuration, both CPUs dedicated entirely to user application
    • LINUX operating system
      • Source and examples provided via GPL license (no charge)
      • ~15 seconds to CPU boot
  • 2 separate DDR3 SODIMMs, one for each FPGA (AB)
    • 533MHz, 1066 MB/s
    • PC3-8500 or better
    • 64-bit, with addressing/power to support 4GB in each socket
    • DDR3 Verilog/VHDL reference design provided (no charge)
    • DDR3 SODIMM data transfer rate: 68Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • Mictor, USB PHY, Extra Interconnect
  • Three independent low-skew global clock networks
    • G0, G1, G2
    • Three, high-resolution, user-programmable synthesizers for G0, G1, G2
      • Silicon Labs Si5326: 2kHz to 945 MHz
    • User configurable via Marvell uP RS232, USB, PCIe, or Ethernet
    • Global clocks networks distributed differentially and balanced
  • Flexible customization via daughter cards using two expansion connectors
    • 400-pin FCI MEG-Array connector
      • Non proprietary, readily available, and cheap
    • 96 LVDS pairs + clocks (or 186 single-ended)
    • 650 MHz on all signals with source synchronous LVDS (with -2 speed grade)
    • Signal voltage set by daughter card (+1.2v to +2.5V)
    • Reset
    • Supplied power rails (fused):
      • +12v (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using LVDS (up to 10x)
  • Fast and Painless FPGA configuration
    • USB, PCIe, Ethernet, JTAG
    • Stand-alone configuration with USB stick or on-board NAND FLASH
    • Configuration Error reporting
    • Accelerated configuration readback for advanced debug
  • RS232 port for embedded FPGA-based SOC uP debug
    • Accessible from all FPGAs via separate 2-signal bus
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope and other third-party debug solutions
  • Status FPGA-controlled LEDs
    • Enough illumination to sterilize refrigerator door handles.


The DNV6_F2PCIE is a complete logic prototyping system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. The DNV6_F2PCIE is hosted in a 4-lane PCIe bus (GEN1), but can be used stand-alone and configured via USB or Ethernet. A single DNV6_F2PCIE configured with 2 Xilinx Virtex-6, LX760s can emulate up to 11 million gates of logic as measured by a reasonable ASIC gate counting standard. This gate count estimate number does not include embedded memories and multipliers resident in each FPGA. One hundred percent (100%) of the Virtex-6 FPGA resources are available to the user application. The DNV6_F2PCIE achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx's 40nm Virtex-6 family. Any subset of FPGAs can be stuffed and we can accommodate any combination of speed grades in any FPGA position.

Virtex-6 FPGAs from Xilinx

The DNV6_F2PCIE uses high I/O-count, 1760-pin, flip-chip BGA packages. The largest device, the LX760, has 1200 I/Os and all are utilized. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGAs. FPGA to FPGA busses are routed, tested, and characterized LVDS and run at 650 MHz+ (which is 1.3 Gb/s when used in DDR mode and assumes -2 speed grade). Single-ended at the reduced speed of 225MHz is characterized and tested. Example designs utilizing the integrated I/O shift registers (ISERDES/OSERDES) with DDR for pin multiplexing are included.

Two 40-pin busses (NMB[A..B]) are connected from the configuration FPGA (Config FPGA) to each field FPGA (A and B). The connection to the Config FPGA allows for data movement via USB, Ethernet, PCIe and SATA to any/all FPGAs. 100% of the resources of the two field Virtex-6 FPGAs is dedicated to the user application.

Two possible Virtex-6 FPGAs can be stuffed in the A, and B positions. You are free to mix and match any FPGA with any available speed grade for each position from the following list (fastest to slowest):

LX760-2, -1, -1L

When stuffed with two LX760s, the DNV6_F2PCIE is capable of prototyping >11 million gates of ASIC logic with plenty of resource margin.

The Marvell MV78200 Discovery™ Dual CPU

A **Monster** for data movement and manipulation

Easy FPGA configuration is a required feature of large, multi-FPGA boards. We use an onboard CPU to handle this function. We choose a Marvell MV78200 from the Discovery™ Innovation CPU family. Bluntly stated, this CPU is massive overkill for the mundane task of FPGA configuration. The MV78200 comes in a variety high performance interfaces, and all can be utilized to your advantage.

Dual Sheeva™ CPUs, 1GHz with floating point

First and foremost are dual CPUs. And after we are done configuring the FPGAs we dedicate both CPUs to your application. The CPUs in the MV78200 are Marvell Sheeva™ cores, which are ARM v5TE compliant. The CPUs are clocked at 1GHz and each processor has a single and double precision floating point unit. A fixed 1 GB, DDR2 memory is standard and is useful for large amounts of high speed data buffering. The memory is organized as 128M x 64 and clocked at the full frequency allowed: 400MHz (800 MHz effective with DDR). This DDR2 bank is shared between the two CPUs. Boot code is resident in an SPI FLASH, and application code is downloaded via any port: PCIe, USB, and Ethernet. We ship LINUX as the standard operating system. Options exist for VxWorks and other real-time operating systems. Contact the factory for more information.

PCI Express

The Marvell 78200 has two 4-lane GEN1 PCIe ports (2.5 GHz). The first, PORT0, is connected to the fingers on the circuit board and is used as the default approach to hosting the DNV6_F2PCIE. Full master mode is supported and multiple DMA engines ease the task of high speed data movement to/from any port. Multiple DNV6_F2PCIes can be placed in a single backplane, but be aware that this product may take two slots due to the heat sinks required.

The second 4-lane PCIe port, PORT1, is connected FPGA-Q (Virtex LX50T-2). We ship a full PCIe bridge in FPGA-Q, enabling data movement between the MV78200 and FPGA-Q at the fastest performance 4-lanes of GEN1 PCIe allows. Note that the MV78200 is a non-transparent PCIe bridge, so some driver support in the MV78200 is necessary. We, of course supply these drivers for no cost.

Two Serial-ATA Ports (SATA II)

The MV78200 has two Serial-ATA Generation 2i (SATA II) ports, each capable of running at 3.0 Gb/s. SATA is intended for high speed data transfer to/from a hard drive. Connectors are provided for both of these SATA ports, enabling a direct connection to external hard drives. Both FPGA A and FPGA B have dual SATA connectors connected to rocketI/O MGTs. With SATA IP integrated into the FPGA logic, SATA cables connected can provide additional high-speed data paths between the field FPGAs and the Marvell processors. Note that the MV78200 has specialized enhanced DMA (EDMA) engines for SATA and a dedicated 512-byte buffer for each channel. Examples of all possible data movement options, with source, are included.

GbE — 802.3 Gigabit Ethernet

The MV78200 has gigabit Ethernet ports. One (of the 4 available) is connected to an external PHY with an RJ45 connector. So, 10/100/100-baseT networking is standard. This is the most popular interface for stand-alone hosting and an easy way to get large amounts of data to/from the DNV6_F2PCIE.

Daughter cards for customization and expansion

A 400-pin FCI MEG-Array connector is attached to both FPGAs, allowing for customization with daughter cards. This is a non-proprietary, industry standard connector and the mating connector is readily available. We can provide the mating connector to you at our cost. We are not fans of proprietary, hard-to-get, outrageously priced expansion connectors. The 192 signals (96 pairs) to/from each of these MEG-Array expansion connectors are routed differentially and can run at the limit of the Virtex-6 FPGA I/Os: 650 MHz (with -2 speed grade). Clocks, resets, and presence detection, along with abundant (fused) power are included in each connector.


Two separate DDR3 SODIMM sockets are connected to each FPGA. This style of SODIMM is 64-bits. Each socket is tested to 533MHz with a PC3-8500 DDR3 SODIMM. Standard, off-the-shelf DDR3 memory SODIMMs work fine and we can provide these for a small charge. The maximum memory size is probably 4GB per SODIMM socket in the short term. We have developed alternative SODIMM’s that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, mictors, USB PHYs, DDR2, RLDRAM I/II, and others. As always, reference material such as a DDR3 SDRAM controller is included (in Verilog, VHDL) at no additional cost.

Easy Configuration via PCIe, USB, or Ethernet

If the DNV6_F2PCIE is hosted via PCIe, USB, or Ethernet, FPGA configuration occurs via the host under the control of one of the Marvell CPUs. If the board is used standalone, the FPGA configuration files are copied onto a USB stick (provided) and FPGA configuration occurs at power up after the Marvell processors have booted (~15 seconds or so). Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process in the case of errors. Multiple LED's provide instant status and operational feedback.

Status LEDs, Debug

The DNV6_F2PCIE contains strong enough illumination to kill the bacteria on a refrigerator door handle, although using the product for this purpose isn't terribly cost effective. When testing this sterilization feature, make sure an adult is present and wear eye protection. Since these LEDs are user controllable from the FPGAs, they can be used as visual feedback for debug purposes. A JTAG connector provides an interface to ChipScope and other third party debug tools.

Specs of FPGAs Available on the DNV6_F2PCIE

Related Documents

Related Resources

Alternate Memory: