Products

DN9200K10PCI

Xilinx Virtex-5 Based ASIC Prototyping Engine

  • PCI-hosted logic prototyping system with 1-2 Xilinx Virtex-5 FPGAs in FF1760 package (slowest to fastest):
    • XC5VLX110 -1,-2,-3
    • XC5VLX155 -1,-2,-3
    • XC5VLX220 -1,-2
    • XC5VLX330 -1,-2
  • 100% FPGA resources available for user application
  • Nearly 4M ASIC gates (LSI measure) with 2 LX330s
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 400Mhz DDR LVDS (800Mb/s) chip-to-chip, can be used single-ended
    • Reference designs for integrated I/O pad ISERDES/OSERDES
  • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Main Bus (MB)
  • 36 signals
    • Single-ended
    • Connects to both FPGAs and Config FPGA
  • 2 DDR2 SODIMMs (250MHz)
    • 64-bit data width, 250MHz operation
    • PC2-4200
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor, DDR1
  • SODIMM Daughtercard expansion
  • Seven board-level global clock networks
    • Three separate programmable synthesizers
    • User configurable via CompactFlash, USB, JTAG, or PCI
    • Global clocks networks distributed differentially and balanced
    • Single-step clocking available on three global clock network
  • Flexible customization via daughter cards
  • Fast and Painless FPGA configuration
    • CompactFlash, PCI, JTAG, and/or USB
    • Integrated sanity checks on configuration files
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro
    • Accelerated configuration readback
  • Enough status LEDs to cure SAD (Seasonal Affective Disorder) in a Yak.
  • Convert MEG Array expansion connectors to interconnect with the DNMEG_Intercon. Add 186 single-ended OR 93 pairs LVDS:
    • FPGA A to B