DN9000K10PCIe-8T
Xilinx Virtex-5 Based ASIC Prototyping Engine

- PCI Express (8-lane) logic prototyping system with 2-6 Xilinx Virtex-5 FPGAs
- XC5VLX330 -1, -2 (FF1760)
- Xilinx Virtex-5T for PCIe interface and controller
- PCIe GEN1 rev 1.1 with LX50T (8 lanes)
- PCIe GEN2 (4 lanes)
- 100% FPGA interconnect is single-ended or LVDS
- Nearly 12M ASIC gates (LSI measure) with 6 Virtex-5 LX330s
- FPGA to FPGA interconnect is single-ended or LVDS
- 450Mhz LVDS chip to chip (900 MB/s)
- Slightly slower when used single-ended (~225MHz)
- Reference designs for integrated I/O pad ISERDES/OSERDES
- 10x pin multiplexing per LVDS pair
- Greatly simplified logic partitioning
- Source synchronous clocking for LVDS
- Main Bus (MB) connects all LX FPGAs (164 signals)
- 6 separate DDR2 SODIMMs (250MHz)
- 1 SODIMM for FPGAs A,B,F,D
- 2 SODIMMs for FPGA C
- 64-bit data width, 250MHz operation
- PC2-4200 or better
- Addressing/power to support 4GB in each socket
- DDR2 Verilog/VHDL reference design provided (no charge)
- DDR2 SODIMM data transfer rate: 32Gb/s
- Alternate pin compatible memory cards available (consult factory for availability):
- SRAM: QDR, ASYNC, STD, or PSRAM
- FLASH
- DRAM: SDR, DDR1, PSRAM or RLDRAM
- Mictor
- Extra Interconnect
- Eight independent low-skew global clock networks
- G0, G1, G2, M48, EXT0, EXT1, FBB, FBE, REF250
- Three, high-resolution, user-programmable synthesizers for G0, G1, G2
- User-configurable via CompactFLASH, USB, and/or PCIe
- Global clocks networks distributed differentially and balanced
- Three independent single-step clocks
- Up to three independent external clocks inputs (single-ended or differential) can be injected onto low-skew global clock networks
- Flexible customization via daughter cards
- 3 daughter card locations: FPGAs D,E,F
- 400-pin FCI MEG-Array connectors
- 93 LVDS pairs + clocks (or 186 single-ended)
- 450MHz on all signals with source synchronous LVDS
- Signal voltage set by daughter card (1.2v to 3.3V)
- Reset
- Supplied power rails (fused):
- +12v (24W max)
- +5V (10W max)
- +3.3V (10W max)
- Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)
- Fast and Painless FPGA configuration
- CompactFLASH, USB, PCIe, JTAG
- Configuration Error reporting
- Accelerated configuration readback
- RS232 port for embedded uP debug
- Accessible from all FPGAs via separate 2-signal bus
- Full support for embedded logic analyzers via JTAG interface
- 90 status LEDs: enough illumination to disturb the circadian cycle of a Sun fish (DCCSF).