(Standard configuration in blue)
(Optional in red)

• 32/64-bit, +3.3V, PCI/PCIX-based PWB.
• Single VirtexII-Pro FPGA in FF1704
  • 2vp70, 2vp100.
• Four external independent SSRAMs
  • 512k/1M/2M x 36
  • pipeline or flowthrough
  • ZBT or non-ZBT
• Four independent DDR SDRAM banks
  • 4 banks 16M/32M x 16
• Two independent external FLASH memories
  • 4M x 16
• 10 High Speed serial ports
  • 1 GigE Fiber (4 MGTs) (requires -6 speed grade)
  • 2 HSSDC2 – Infiniband (2 MGTs)
  • 2 SATA (2 MGTs)
  • 2 SMB (2 MGT)
• One 200-pin high-speed connectors for awesome signal integrity
  • custom daughter cards
  • observation daughter cards (such as DN3k10SD or DNPMC104)
  • We recommend using the Daughter Card Extender when using 200-pin daughtercards.
• 5A onboard linear regulator for +1.5V
  • 5A onboard switcher for +2.5V and Vtt
  • 5A switcher for +3.3V
• Two PowerPC 405 Cores
  • Embedded 300+ MHz Harvard Architecture
  • Hardware Multiply/Divide Unit
  • Thirty-Two 32-bit General Purpose Registers
  • 16 KB 2-Way Set-Associative Instruction Cache
  • 16 KB 2-Way Set-Associative Data Cache
  • Memory Management Unit (MMU)
  • Timer Facilities
  • Two dedicated external JTAG connectors for uP trace/debug
• Four RS232 ports for PowerPC processor visibility
  • 2 Tx/Rx
  • 1 Tx only
• Standalone operation via separate power connector
  • +3.3V not needed on backplane
• Fast/Easy FPGA configuration via standard SmartMedia FLASH card
  • Microprocessor controlled (Atmega128L)
  • RS232 port for configuration/operational status and control
  • Fastest possible configuration using SelectMap parallel
    • 2vp70 configures in 1 second
  • Sanity checking programs for bit files eases configuration hassles
• 6 low skew clocks distributed to FPGAs and test connector:
  • 2 CY7B994 RoboClockII PLLs for the best clock distribution
  • 1 FCT3805 low-skew clock driver (non-PLL)
  • 2 user-selectable socketed oscillators
  • PCI/PCI-X clock
  • 1 dividable clock via CPLD
• Boatloads of reference stuff included (FREE)
  • 32-bit target PCI design (Verilog/VHDL)
  • 32-bit master/target OpenCore PCI (Verilog)
  • SDRAM controller (Verilog/VHDL)
  • DDR SDRAM controller (Verilog/VHDL)
  • PowerPC ‘Hello World’
  • UARTs
  • DOS-based utilities
  • Board test(s)
  • PCI Drivers (with C code)
    • Windows XP, ME, 2000, 98, NT
    • LINUX, Solaris
• Full support for embedded logic analyzers
  • ChipScope, ChipScope PRO
  • Identify™ from Synplicity
• 162 signals for observation/debug
  • Fully compatible with the DN3k10SD