ASIC Prototyping Engine

  • Single FPGA Virtex II
  • 32/64-bit, +3.3V, PCI/PCIX-based PWB with one Xilinx VirtexIIâ„¢ FPGAs (FF1152 BGA)
    • Initial availability: 2V6000/2V8000/2V4000
  • Flexible, abundant and configurable embedded memory:
    • Up to 331 Kb dual-port SelectRAM (assuming XC2V6000)
    • Plus up to 135 Kb Distributed RAM (assuming XC2V6000)
  • Fast/Easy FPGA configuration via standard SmartMedia FLASH card
    • Microprocessor controlled
    • RS232 port for configuration/operational status and control
    • Fastest possible configuration using SelectMap
    • Sanity checking programs for bit files eases configuration hassles
  • 5A on-board linear regulator for +3.3V and +1.5V
    • Standalone operation via separate power connector
    • +3.3V not needed on backplane
  • 6 low skew clocks distributed to FPGA and test connectors:
    • 2 CY7B993/4 RoboClockII PLLs
    • 2 socketed oscillators
    • PCI Clock
    • 1 dividable clock via CPLD
  • Direct Support for Synplicity's Certify TDM interconnect multiplexing
  • Robust observation/debug with 450+ connections for logic analyzer
    observability or for pattern generator stimulus
  • Status LEDs
  • User designed daughter PWB for custom circuitry and interfaces
    • HW locking mechanisms for IP protection via CPLD
    • Hosted in a 66/100/133 MHz PCI/PCIX slot or standalone
  • Four external memories included:
    • 3 512K x 36 Pipeline/Flowthrough SSRAM
    • 512 Mbyte SDRAM DIMM (upgradeable to 8 GB)


The DN3000k10s is a complete logic emulation system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN3000k10s can be hosted in 32/64-bit PCI/PCIX slot, or can be used stand-alone. A DN3000k10s can emulate up to 500,000 gates of logic as measured by LSI. The DN3000k10s achieves high gate density and allows for fast target clock frequencies by utilizing Xilinx's VirtexII™ family for logic and memory. High I/O-count, 1152-pin, flip-chip BGA packages are employed allowing for abundant, fixed interconnect between the FPGA and headers. A total of 664 bus pins are provided on the top of the PWB for logic analyzer-based debugging, or for pattern generator stimulus. Custom daughter cards can be mounted to these connectors as a means of interfacing the DN3000k10s to application-specific circuits. A reference 32-bit PCI target design and test bench is provided (in Verilog) at no additional cost.

Easy Configuration via SmartMedia
The configuration bit files for the FPGAs are copied onto a 16-megabyte SmartMedia FLASH card (provided) and an on-board microprocessor controls the FPGA configuration process. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, helping to avoid the time consuming process of debugging the configuration process. FPGA configuration occurs at close to the fastest possible SelectMap frequency - 48MHz. Eight LEDs provide instant status and operational feedback. Two of these LEDs are connected to the CPLD and can be user-configured.

Related Information
To add Gigabit Ethernet capabilities to this board, we recommend the MP1000TX Gigabit Ethernet Daughter Board from Metanetworks.

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Headers and Connectors

PLL Headers
Daughter Card Connectors

Battery Connector

Smart Media Socket

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