ARM Core Tile Interface Daugher Card

  • Interface connecting a RealView® ARM Core Tile to any DINI FPGA board
    • ARM9: CT926EJ-S
    • ARM11: CT1136JF-S
  • Prototype up to 50M ASIC gates (with DN7020k10)
  • ARM Microprocessor/SOC Peripherals:
    • Through Xilinx Spartan-3 FPGA from ARM AHB bus (on HDRX):
      • 6-pin PS2 DIN for Mouse and Keyboard
      • SDRAM, 2 Micron MT48LX16M16A2, 16M x 32
        • PC100/PC133
      • FLASH, Atmel AT49BV320D, 2M x16
      • SSRAM, Cypress CY7C1380D, 512k x 36
      • Audio AC-97 v2.1 SoundMAX Codec (Analog Devices AD1881A)
        • Intel standard Front Panel Audio Header
        • Jack for CDROM Audio
      • RS232 port for uP visibility and debug
    • Through host 400-pin MEG-Array connector:
      • USB2.0 Phy (SMSC USB3300)
        • device, host, or On-The-Go device (OTG)
      • Gigabit Ethernet transceiver (Vitesse VCS8601)
        • 10base-T/100base-T/1000-base-T
        • RGMII interface
  • Xilinx Spartan 3 FPGA
    • CoreTile interfaces:
      • HDRX: AHB bus
      • HDRY: LEDs, GPIO, PISMO memory expansion
      • HDRZ: ARM ICE and debug
    • Largest FPGA in family: 3S5000-4 (FG900)
      • 66k FFs
      • 240 kbytes BlockRAM
      • Full support for embedded logic analyzers via JTAG interface
        • ChipScope, ChipScope Pro and other third party debug solutions
  • Stand-alone operation with optional external power supply
  • 32 status LEDs — more than enough illumination to function as a fog light


ARM supplies a circuit board with a processor test chip that has an ARM9 (or ARM11) within. ARM calls this product a RealView® Coretile. The DNMEG_ARM_TILE is an intermediate host for a CoreTile adding the features and interfaces needed to make the ARM processor on the CoreTile useful for prototyping. The combination of the DNMEG_ARM_TILE with the CoreTile is mounted on an ASIC FPGA board from The DINI Group, enabling full speed system prototyping and debug of high gate count ARM-based systems. With a separate power supply, the DNMEG_ARM_TILE/CoreTile combo can be used stand alone.

The CoreTile for ARM926EJ-S, for example, contains an ARM926EJ-S processor inside a test chip. The ARM9 processor configuration signals and a multiplexed AHB bus are connected to the board headers (HDRX). This CoreTile is mounted onto the DNMEG_ARM_TILE, which is, in turn, mounted onto any of the ASIC prototyping boards available from the DINI Group.

The AHB bus from HDRX is connected to the Spartan-3 FPGA and the 400-pin MEG_Array expansion header. When DNMEG_ARM_TILE/CoreTile combo is installed on a DN9000k10, more than 32 million ASIC gates can be prototyped. CoreTiles can be stacked for multi-core prototyping. Three of the DNMEG_ARM_TILE/CoreTile combos can be mounted on our blockbuster DN7006k10PCIe-8T ASIC prototyping board. The popular DN9000k10 or DN7020k10 can host 6 separate DNMEG_ARM_TILE/CoreTile combos.

Memory expansion via PISMO is enabled to the CoreTile via HDRY. The Spartan-3 FPGA connects to most signals on this connector. User-controllable LEDs (32 in total) and 20 general purpose I/Os (GPIO) are also connected to the FPGA and HDRY.

Additional memory expansion via PISMO is enabled to the CoreTile via HDRZ. The Spartan-3 FPGA also connects to all signals on this header. The DNMEG_ARM_TILE provides the proper connector for the variety of ARM in-circuit-emulators (ICE) and debug equipment via ARM ICE debug port.

CoreTiles are available from ARM and must be purchased separately. We will try to stock some of the more popular variations here in La Jolla. Call or email our sales staff to determine availability.

Xilinx Spartan-3 FPGA: 3S5000
On the DNMEG_ARM_TILE the AHB bus from the ARM processor is connected to a Xilinx Spartan-3 FPGA. We use the 3S5000-4 as the standard stuffing option. All resources of this Xilinx FPGA are available to the user application. This is a fairly large FPGA, containing 66,560 FF/LUT pairs and 240kbytes of block RAM. By a conservative measure this FPGA alone can prototype 560k ASIC gates excluding memory and multipliers. This ASIC gate number can be increased in the short term to as much as 50M ASIC gates via a DN7020k10. When Altera releases the Stratix-4 family, this number will increase to >100M gates.

SDRAM – PC100/PC133
Two Micron synchronous DRAMs (MT48LC16M16A2) are connected to the FPGA in a 16M x 32 configuration. These SDRAMs are PC100/PC133 compliant. A sample SDRAM controller is provided in Verilog. The memory is mapped into ARM address space and read/write access code is provided.

A single Cypress pipelined SSRAM is connected to the FPGA in a 512k x 36 configuration. A sample controller (in Verilog) is provided.

A single 32 megabit FLASH memory from Atmel is connected to the FPGA in a 2M x 16 configuration. It is hard to describe a single FLASH chip in an exciting manner. This Atmel device has all the features you would expect.

AC97 Audio
An Analog Devices AD1881A is connected to the FPGA. A CD Audio, Line Out, and Headphone IN connector is provided. The AD1881A meets the Audio Codec ’97 2.0 and 2.1 Extensions. In addition, the AD1881A SoundMAX Codec is designed to meet all requirements of the Audio Codec ’97, Component Specification, Revision 1.03. The AD1881A also includes some other Codec enhanced features such as the built-in PHAT Stereo 3D enhancement. This peripheral could really annoy that guy in the next cubicle.

USB IP logic can be thoroughly tested in the target environment. An SMSC USB3300 is compliant to the USB2.0 specification and has a UTMI+ interface. Provided the correct IP is implemented, this USB interface is capable of operating as a device, host, or On-The-Go (OTG) device.

Ethernet PHY – 10/100/1000base-T
With an appropriate MAC, a Vitesse VSC8601 Ethernet PHY provides 10/100/1000base-T Ethernet.

Specs of FPGAs Available on the DNMEG_ARM_TILE

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