Daughtercard form-factor
Virtex-5T Based
ASIC Prototyping Engine

  • 8-lane PCI Express daughter card with Xilinx Virtex-5 FPGA (GEN1 and GEN2)
    • 12 GTPs: LX50T, LX85T, SX50T (-1, -2, -3)
    • 16 GTPs: FX70T, LX110T, LX155T, SX95T, FX100T (-1, -2, -3)
  • 1, 4, or 8-lane PCIe hosting of DINI ASIC emulation products (with DNMEG_CBL-D)
  • 1, 4, or 8-lane PCIe peripherals to DINI ASIC emulation products (with DNMEG_CBL-U)
  • Emulation and prototyping of PCIe SOC/IP:
    • PCIe to PCIe bridges (GEN1 and GEN2)
      • Dual 1/4/8-lane PCIe to 1/4/8-lane PCIe
      • Triple 1/4/8-lane PCIe bridge
    • PCIe to 1000Base-T, 100Base-T, or 10Base-T
    • PCIe to Fibre Channel
    • PCIe to SAS/SATA
    • PCIe to Inifiniband
  • (Optional) PCIe clock slow down IP
  • Fixed PCIe controller provided
    • Master-moding with drivers included
    • 100% FPGA resources available for user application if fixed PCIe controller not used
  • Nearly 660k ASIC gates (LSI measure) with LX110T
    • Add up to 32 million ASIC gates with the DN9000k10
  • DDR2 SODIMMs (250MHz)
    • 64-bit data width, 250MHz operation
    • PC-3200/PC2-4200
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 25.6Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
  • Flexible, abundant clock resources
    • 3 board-level clocks configurable clocks based on the Si5326
    • 2 stuffable low-jitter fixed oscillators
    • Fixed 100MHz and 200MHz oscillators
      • For PCIe and DDR2 clocking
    • Off-board differential clocking
  • Mount to DINI products with 400-pin MEG-Array connectors
    • 93 LVDS pairs + clocks (or 186 single-ended)
    • 450MHz on all signals with LVDS (slower when used single-ended)
    • Reset, presence detect
    • Pin multiplexing to/from motherboard using ISERDES/OSERDES and LVDS (up to 10x)
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
    • Source synchronous clocking
  • Fast and Painless FPGA configuration with integrated PROM
  • RS232 port for embedded uP debug
  • Mictor for logic analyzer debug
  • Battery socket for configuration bitfile encryption
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro and other third party solutions
  • Enough status LEDs with which to pull over a speeding Porsche
  • Gigabit serial I/O interfaces using GTP transceivers:
    • SMA connectors for off-board cabling to 4 TX/RX channels
      • PCI Express
      • SATA
      • Serial RapidI/O
      • Aurora
    • iPASS for x1, x4, x8 PCI Express cabling
    • Clocking options for standard serial communication protocols
    • Ability to use embedded Ethernet MAC with SFP and SMA connectors
    • 16 GTP FPGAs only:
      • 1 Small form factor (SFP) modules
        • 1x Fibre Channel, 1G Ethernet, SATA, et al.
      • DisplayPort(x4)
        • source and sink
        • compatible with Xilinx DisplayPort IP core


The DNMEG_V5T_PCIE is a daughter card that adds a PCI Express interface to the many FPGA ASIC prototyping boards from The DINI Group. The PCIe interface can be configured as 1, 4, or 8-lanes. When using Xilinx Virtex-5 LXT or SXT devices, the board is fully compatible with 2.5Gb/s GEN1 PCIe. Gen2 (5.0Gb/s) PCIe functionality is fully supported using the Virtex-5 FX70T-2 (or FX100T-2). When used as a daughter card to the DN9000k10PCIe-8T, an 8-lane PCIe <-> PCIe bridge can be emulated with either (or both) sides GEN1 or GEN2. A treble PCIe bridge can be constructed with two of these daughter cards. The massive 32 million gate DN9000k10 can be converted to a high data bandwidth PCIe master (or peripheral).

A full featured PCIe controller is provided standard. The controller includes master moding DMA. 'C' source examples along with drivers are included.

The DNMEG_V5T_PCIE mounts to a DINI base-board using the 400-pin FCI MEG-Array expansion connectors. A small PCIe buffer card (DNPCIe_CBL-D or DNPCIe_CBL-U) is inserted into a host/peripheral PCIe slot and the DNMEG_V5T_PCIE is connected via two, 4-channel iPASS cables. The DNMEG_V5T_PCIE can be used stand-alone.

Xilinx Virtex-5 FPGA

In its standard configuration, the DNMEG_V5T_PCIE is stuffed with a Xilinx Virtex-5 LX110T-1. The LX110T is a relatively large FPGA, containing 69,120 LUT/FF pairs, along with 64, 25x18 multipliers. Five megabytes of internal block memory (296, separate 18kbit blocks) enable the implementation of large scratchpad memories and FIFOs - vital for PCIe applications. The Virtex-5 family has 6-input lookup tables (LUTs), making this FPGA family extremely logic rich. The larger LUT works to reduce the number of logic layers which increases the frequency of operation. Optional stuffing options include the SX50T or SX95T, which has a greater number of embedded multipliers and is optimized for DSP-type applications.

RocketI/O GTP

Eight of the RocketI/O GTP transceivers are used for the 8-lane PCIe interface (via the iPASS cables). Four of the channels are connected to SMA connectors (16 SMA connectors total). The SMA connectors can be used to create a large list of high speed serial interfaces. The most common is Infiniband. A DisplayPort physical interface is added when this board is stuffed with the LX110T or FX70T, SX95T, LX155T, or FX100T. Four RocketI/O GTP channels are needed. An SFP socket shares a RocketI/O GTP with DisplayPort. A wide range of SFP modules is available. The list includes, but is not limited to, 10/100/1000Base-T, SATA, Fibre Channel. The SMAs along with DisplayPort/SFP enable all sorts of PCIe bridges to be emulated: PCIe <-> SATA, PCIe <->1000BaseT, etc.


A single DDR2 SODIMM socket is connected to the FPGA. This SODIMM socket is tested to 250MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMMs (PC2-5300) work nicely and we can provide these for a small charge. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, RLDRAM, SDR SDRAM, mictors, DDR1, DDR3, interconnect, USB Phy, and others. The board includes a DDR2 controller in VHDL and Verilog, and example RocketIO GTP implementations in Verilog, with VHDL is available on request.

Other Features

A Mictor with 28 FPGA connections enables debugging with Tektronix or Agilent Logic Analyzer. Eight user LEDs can be used for all sorts of FPGA-controller visual feedback. The LEDs are bright enough to pull over speeding exotic cars if sequenced correctly. This law enforcement application has not been completely tested.

Connecting Virtex 5 MGT to various media

100Base-FX Cisco GLC-GE-100FX ($179
100Base-BX Cisco GLC-FE-100BX-U ($136
100BASE-T ("RJ45") Linksys MFEFX1 ($90
100Base-T ("RJ45") Black Box LFP301 ($108
("Optical Gigabit Ethernet")
Finisar FTLF8519P2BNL ($74
10GBASE-CX4 ("Infiniband")
("user connector on board")
10GBASE-LR,-SR,-LW,-ZW SFP+ Direct Attach
10GBASE-T ("RJ-45") must connect to a 10Gbs repeater ("Media Converter")
SATA Finisar Xgig-LD30SA
Fibre Channel 4.25Gbs LC Cisco DS-SFP-FC4G-SW ($73.00
Fibre Channel 8Gbs requires SFP+ module. Please call.
Fibre Channel 10Gbs requires SFP+ module. Please call.
And a Cisco AG861A

Specs of FPGAs Available on the DNMEG_V5T_PCIe

Note: Product comes with iPASS 4-lane PCIe cable cages on connectors

Board with cables attached

DNPCIe_CBL Downstream, recommended accessory

DNPCIe_CBL Upstream, recommended accessory

Board connected to Downstream accessory via iPASS cables

Related Documents

Related Resources

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