Daughter Card with Virtex-4 LX/SX FPGA
2 channel A/D (210 MSPS)
2 channel D/A (160 MSPS)
- 2 channels of Analog to Digital Conversion (2x of AD9430)
- 12-bits, 210 MSPS
- 2 channels of Digital to Analog Conversion (AD9777)
- 16-bits, 160 MSPS
- Xilinx Virtex-4 FPGA (FF1148):
- stuffing option for LX40, LX60, LX80, LX100, or SX55
- -10, -11, or -12 speed grade
- 100% FPGA resources available for user application
- Stand-alone operation with ATX power supply
- DDR2 SODIMM (200MHz)
- 64-bit data width, 200MHz operation
- PC2-3200/PC2-4200 or better
- Addressing/power to support 4GB
- DDR2 Verilog/VHDL reference design provided
- DDR2 SODIMM data transfer rate: 25.6Gb/s
- Alternate pin compatible memory cards available:
- Click here to see the compatibility chart for DNSODM products
- QDR SSRAM, FLASH (with SSRAM), SSRAM
- RLDRAM, Mictors, Standard SRAM
- Two 400-pin Meg-Array connectors (top and bottom of PWB)
- Daughter card to all of our DNMEG-array enabled main boards
- 93 LVDS signal pairs + clocks (or 186 single-ended)
- 350MHz on all signals with LVDS (200MHz single-ended)
- Pin multiplexing to/from mother card using ISERDES/OSERDES and LVDS (up to 10x)
- DNMEG_Obs_400 Observation Daughter Card can be mounted to top connector
- RS232 port for embedded uP debug
- Serial Flash (4-megabit): AT45DB041B
- Mictor for direct connection to HP or Tektronix Logic Analyzer
- Multiple clocking options for ADCs and DAC
- Dual factory-installed clock oscillators OR SMAs for external clock
- PLL Clock Synthesizer
- Full support for embedded logic analyzers via JTAG interface
- ChipScope, ChipScope Pro
- Enough status LEDs to blind three overfed naked mole-rats (Heterocephalus glaber)
- Now 100% RoHS!
The DNMEG_AD-DA is intended to be a peripheral daughter card to our ASIC emulation products, but can be used stand-alone with an inexpensive ATX power supply.
FPGA - Xilinx Virtex-4
A single Xilinx Virtex-4 FPGA in the FF1148 package is provided. All A/D and D/A data is routed through the FPGA. An FPGA in any available speed grade from the following list can be utilized: LX40, LX60, LX80, LX100, SX55. We intend to stock small quantities of the most popular stuffing options so contact the factory for availability.
All FPGA resources are available to the user's application. In Virtex-4, this includes the logic, embedded memory, multipliers, XtremeDSP slices, and DCMs. The SX55, which contains 512 18x18 multipliers, excels at FPGA-based signal processing. The LX FPGAs are logic intensive with the LX100, the third largest of the Virtex-4 FPGAs, containing 98k FFs. The LX100 can emulate up to 1.4 million gates of ASIC logic. The LX40 with 37k FFs is the lowest cost stuffing option. The LX160 can be stuffed, but the EEPROM is not large enough to store the configuration bit file. The LX160 is a valid option if you are willing to manually configure the FPGA via JTAG.
The Virtex-4 FPGA is SRAM-based, so its brains fall out when power is off. The configuration bit file is stored in an on board EEPROM (XCF32P) and configuration automatically occurs at the initial application of power. Different configuration files are loaded in the EEPROM via JTAG cable (not provided). The FPGA is not dynamically reconfigurable from the 400-pin host connector.
Dual 12-bit A/D Converters
Two Analog Devices AD9430 devices provide for two channels of 12-bit analog to digital conversion at sampling rates up to 210 MSPS. The AD9430 devices have on-chip references and internal track-and-hold circuitry. The data bus from AD9403s to the FPGA is source synchronous LVDS and comfortably runs at the full 210 MSPS frequency in the slowest speed grade Virtex-4 FPGA. Clocking is very flexible and the block diagram is probably the best way to understand the functionality. Each analog to digital converter can be clocked separately. These clocks can be sourced from a userstuffable oscillator, from an external source via an SMA connector, or from the FPGA. The FPGA gets its clocks from a PLL Clock Synthesizer (ICS8442), from the motherboard via the 400-pin connector, or from a daughter card such as the DNMEG_obs MEG Array Observation Daughter Card.
Dual 16-bit D/A Converters
A single Analog Devices AD9777 provides two channels of 16-bit digital to analog conversion at a sampling rate up 160 MSPS. All of the AD9777 programmable functionality is available to the user via the SPI port connected to the FPGA. This includes 2x/4x/8x interpolation, direct 70 MHz IF transmission, twos complement/straight binary encoding, and channel gain control. Clocking is provided via one of several possible clock sources as shown in the block diagram.
Other cool stuff
One DDR2 SDRAM SODIMM is provided, allowing the Virtex-4 FPGA to directly address up to 4GB of DDR2 memory. Alternative SODIMMs are available, including QDR SSRAM, SSRAM pipeline/flowthrough, NoBL/ZBT, Flash, Mictor connectors, and Micron RLDRAM. The SODIMM socket is tested at 200MHz, and reference designs are provided. Standard, off-the-shelf 200-pin DDR2 SODIMMs (PC3200 or better) work fine.
Eight, FPGA-controlled LEDs provide for visual status. Although no laboratory testing was performed, statistical animal models are showing this to be enough illumination to blind three (and possibly four) overfed naked mole-rats (Heterocephalus glaber). A serial 4 Mbit FLASH is available for miscellaneous code and parameter storage. A Mictor connector, which has 34 FPGA signals, enables observation via logic analyzers from Tektronix and HP.
- Product Brief [HI - 12MB]
- Product Brief [LO - 1.5MB]
- Block Diagram - [PDF - 16KB]
- Block Diagram -- Clocking - [PDF - 352KB]
- FPGA Selection - [XLS - 16KB]
- Manual - [PDF - 1.39MB]
- AD9430 datasheet - [PDF - 1.8MB]
- AD9777 datasheet - [PDF - 1.8MB]
- MEG Array Daughter Card Interface Description [PDF - 660KB]
- Daughter Card Compatibility Guide [PDF - 63KB]