Super-FinSim is a complete Verilog interchangeable simulator. All Verilog language specifications such as user definition primitiveness ( user Defined Primitive ), specify block, system task, system function, PLI 1.0, and VCF and SDF are supported.

Super-FinSim supports the mixture simulation of the compilation simulation, the event drive interpretive simulation, the compilation simulation, and the interpretive simulation. The user became possible to obtain the correction and the execution turnaround with short high-speed simulation interpretive simulated of the compilation simulation it by this strong simulation environment.

The Fintronic Co. achieved the Verilog simulator that firstly executed event simulation and the cycle simulation in the industry by Super-FinSim. Smart partitioner analyzed and decided to execute simulation with which part of the design description by Enhanced Cycle Simulation(ECS) or apply event simulation for the remainder. Therefore, Super-FinSim doesn't demand special design metholody. Super-FinSim covers precise timing information and the entire fraught Verilog description. The signal and the strength of 'X' and 'Z' are completely supported besides the module of passing delay description and RTL level description can be treated similarly.

Super-FinSim supports a popular waveform display tool. Signalscan of Undertow, Veritools Co. and Design Acceleration Co. are included.
In DA Solution Limited `96 benchmark, FinSim-ECS, the former version of Super-FinSim, was evaluated as the most high-speed simulator in the Verilog simulator. FinSim was evaluated as the most high-speed Verilog simulator on PC platform by the bench mark and "ASIC & EDA".

Super-FinSim can be executed in all popular platforms such as Sun Solaris, HP UX, Windows NT, Winodws 2000, Windows 98, and Windows Me Linux.