<?xml version="1.0" encoding="UTF-8"?>
<feed xmlns="http://www.w3.org/2005/Atom">
   <title>アプリスター</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/" />
   <link rel="self" type="application/atom+xml" href="http://www.applistar.com/atom.xml" />
   <id>tag:www.applistar.com,2010://1</id>
   <updated>2010-01-14T10:02:42Z</updated>
   <subtitle>(株)アプリスターのWebサイト</subtitle>
   <generator uri="http://www.sixapart.com/movabletype/">Movable Type 3.33-ja</generator>

<entry>
   <title>DNMEG_V5T_10G</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/01/dnmeg_v5t_10g.html" />
   <id>tag:www.applistar.com,2010://1.457</id>
   
   <published>2010-01-14T09:33:49Z</published>
   <updated>2010-01-14T10:02:42Z</updated>
   
   <summary>


</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<font color="red"><b>NEW!</b></font>
Meg-Array daughter card adds 10GbE (via SFP+) to any DINI Group FPGA base board.]]>
      <![CDATA[<a href="http://www.applistar.com/DNMEG_V5T-10Gblk_v11.html" onclick="window.open('http://www.applistar.com/DNMEG_V5T-10Gblk_v11.html','popup','width=1650,height=1275,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DNMEG_V5T-10Gblk_v11-thumb.png" width="450"  alt="" /></a><img src="http://www.applistar.com/rohs.png"  width="80" alt="" />]]>
   </content>
</entry>
<entry>
   <title>DNV6F6PCIe</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/01/dnv6f6pcie.html" />
   <id>tag:www.applistar.com,2010://1.456</id>
   
   <published>2010-01-12T11:17:22Z</published>
   <updated>2010-01-14T09:32:56Z</updated>
   
   <summary>




</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<font color="red"><b>NEW! VIRTEX-6!</b></font>
With 6 VIRTEX-6 FPGAs, the <b>DNV6F6PCIe</b> is a complete logic prototyping system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions.]]>
      <![CDATA[<img alt="V6_LOGOr.PNG" src="http://www.applistar.com/V6_LOGOr.PNG" width="100"  /><a href="http://www.applistar.com/DNV6F6PCIe_blckv1111.html" onclick="window.open('http://www.applistar.com/DNV6F6PCIe_blckv1111.html','popup','width=1650,height=1275,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DNV6F6PCIe_blckv1111-thumb.png" width="510" alt="" /></a>]]>
   </content>
</entry>
<entry>
   <title>DNBFC_S12_PCIe</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/01/dnbfc_s12_pcie.html" />
   <id>tag:www.applistar.com,2010://1.455</id>
   
   <published>2010-01-12T10:15:40Z</published>
   <updated>2010-01-14T09:27:34Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<font color="red"><b>NEW! Spartan-6!</b></font>
Algorithm Acceleration System. Twelve Xilinx Spartan-6 FPGAs in the FF484 package. 12 DDR3 SODIMMs (2Gb each). Dedicated PCIe, 4-lane controller (GEN1 or GEN2). Enhanced IP Security with AES and Device DNA protection.]]>
      <![CDATA[<a href="http://www.applistar.com/DNBFC_S12_PCIe_blckv14.html" onclick="window.open('http://www.applistar.com/DNBFC_S12_PCIe_blckv14.html','popup','width=3300,height=2550,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DNBFC_S12_PCIe_blckv14-thumb.png" width="580" alt="" /></a>
<p style="top: -20px; left: -50px; position: relative;" align="right"><b><i>(Bigger, Faster, Cheaper)</i><br>Spartan-6 FPGA Algorithm Acceleration System<br>For High Performance Computing<br>12 Low-cost FPGAs with DDR3 memory<br>Hosted via 4-lane PCI Express (GEN1/GEN2)</b></p>
]]>
   </content>
</entry>
<entry>
   <title>DN-DualV6-PCIe-4</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/12/dndualv6pcie4.html" />
   <id>tag:www.applistar.com,2009://1.454</id>
   
   <published>2009-12-30T07:16:46Z</published>
   <updated>2010-01-12T11:07:12Z</updated>
   
   <summary>

</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<font color="red"><b>NEW! VIRTEX-6!</b></font>
Two Xilinx Virtex-6 FPGAs in the FF1156 package. 2 DDR3 SODIMMs (up to 4GB each) Select any of the following FPGAs: SX475T,SX315T,LX365T,LX240T,LX195T,LX130T. Marvell MV78200 Dual CPU for massive date manipulation and movement.]]>
      <![CDATA[<img alt="V6_LOGOr.PNG" src="http://www.applistar.com/V6_LOGOr.PNG" width="100"  /><a href="http://www.applistar.com/DN-DualV6-PCIe-4_BD_v210.html" onclick="window.open('http://www.applistar.com/DN-DualV6-PCIe-4_BD_v210.html','popup','width=5100,height=6600,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DN-DualV6-PCIe-4_BD_v210-thumb.png" width="450" alt="" /></a>
]]>
   </content>
</entry>
<entry>
   <title>DNDSP_40G</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/12/dndsp_40g.html" />
   <id>tag:www.applistar.com,2009://1.453</id>
   
   <published>2009-12-30T07:13:21Z</published>
   <updated>2009-12-30T10:01:22Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<p>
The DNDSP_40G is a circuit board that is plugged into any PCIe tower or server. Each board has four TMS320C6455 fixed-point digital signal processors, enabling massive fixed-point processing power to be applied to data-intensive applications independent of the host processor. Each DSP has a 128M x 32 DDR memory. Each DSP is connected to a Serial RapidIO (SRIO) Central packet Switch (IDT80KSW0005) with a 4x port. Each port is clocked at the maximum SRIO frequency supported by the CPS and DSP.
</p>
<p>
&nbsp;
</p>
]]>
      <![CDATA[<div align="center">
<span style="font-size: x-small; color: #0000ff">DNDSP_40G<br />
Quad-DSP Farm Cluster Element with Serial Rapid I/O Interconnect</span><a href="http://www.applistar.com/DNDSP_40G_blckv111.html" onclick="window.open('http://www.applistar.com/DNDSP_40G_blckv111.html','popup','width=3508,height=2479,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false">
<img src="http://www.applistar.com/DNDSP_40G_blckv11-thumb.png" alt="" width="550" height="388" />
</a>
</div>
]]>
   </content>
</entry>
<entry>
   <title>DN9200K10PCIe-8T</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/04/post_17.html" />
   <id>tag:www.applistar.com,2009://1.452</id>
   
   <published>2009-04-13T04:51:49Z</published>
   <updated>2009-12-30T08:21:09Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<p>
The DN9200k10PCIe-8T is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN9200k10PCIe-8T is hosted in an 8-lane PCIe slot or can be used stand-alone and configured via USB or Compact FLASH. A single board configured with 2 Xilinx Virtex-5 LX330&#39;s can emulate up to 4 million gates of logic as measured by LSI.
</p>
]]>
      <![CDATA[<a href="http://www.applistar.com/DN9200k10PCIe8T_blockd.html" onclick="window.open('http://www.applistar.com/DN9200k10PCIe8T_blockd.html','popup','width=1045,height=795,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false">
<img src="http://www.applistar.com/DN9200k10PCIe8T_blockd.png" alt="DN9200k10PCIe8T_blockd.png" width="550" />
</a>
]]>
   </content>
</entry>
<entry>
   <title>DN7002k10MEG</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/04/dn7002k10meg.html" />
   <id>tag:www.applistar.com,2009://1.450</id>
   
   <published>2009-04-13T00:45:03Z</published>
   <updated>2009-04-13T05:27:15Z</updated>
   
   <summary>
</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      The DN7002k10MEG is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype system-on-a-chip (SOC) logic and memory designs for a fraction of the cost of existing solutions. It can be used stand-alone or hosted via a USB interface. A single DN7002k10MEG configured with two Altera Stratix III 3SL340s can emulate up to 5 million gates of logic as measured by LSI. This product is pin-compatible with the Stratix IV which will be coming in 2009 and will allow the board to emulate 10.5 million ASIC gates when configured with the 4SE680. Any subset of FPGAs can be stuffed and each FPGA position can be stuffed with any available speed grade.

      <![CDATA[<img src="http://www.applistar.com/7002_bd_A.jpg" alt="7002_bd_A.jpg" width="550" />
<a href="http://www.applistar.com/7002_bd_B_thumb.html" onclick="window.open('http://www.applistar.com/7002_bd_B_thumb.html','popup','width=599,height=447,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false">
<img src="http://www.applistar.com/7002_bd_B_thumb.jpg" alt="7002_bd_A.jpg" width="550" />
</a>
]]>
   </content>
</entry>
<entry>
   <title>EDSFair 2010に出展します</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/04/esec_2009.html" />
   <id>tag:www.applistar.com,2009://1.449</id>
   
   <published>2009-04-09T23:58:19Z</published>
   <updated>2009-12-29T23:13:05Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="999TOP News" scheme="http://www.sixapart.com/ns/types#category" />
   
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<p>
株式会社アプリスターはEDS Fair 2010に出展します。
</p>
<p>
ブース番号　１０６
</p>
]]>
      <![CDATA[<p>
◇会&nbsp;&nbsp;&nbsp; 期&nbsp; 2010年 1月28日(木)～1月29日(金) 10:00～18:00<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<br />
◇出展場所&nbsp; パシフィコ横浜　ブース番号１０６
</p>
<p>
<a href="http://www.edsfair.com/">http://www.edsfair.com/</a>
</p>
<p>
&nbsp;
</p>
<p>
&nbsp;
</p>
]]>
   </content>
</entry>
<entry>
   <title>ベトナムにIT子会社を設立</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2008/12/it.html" />
   <id>tag:www.applistar.com,2008://1.445</id>
   
   <published>2008-12-25T00:56:56Z</published>
   <updated>2009-12-29T23:15:31Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="999TOP News" scheme="http://www.sixapart.com/ns/types#category" />
   
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<p>
株式会社アプリスター　はASIC設計検証サービスやFPGA評価ボードを提供しています。平成２０年１０月にベトナムにIT子会社設立しました。オフショア開発による効率的な設計支援体制を提案しています。ベトナムのトップクラス大学出身者のエンジニアを御社の設計現場に派遣いたします。またiPhone, Android等の携帯アプリを開発いたします。
</p>
<p>
<a href="http://mobile.applistar.com/">http://mobile.applistar.com/</a>
</p>
]]>
      
   </content>
</entry>
<entry>
   <title>ロボット研究会のサポータ企業になりました</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2008/12/post_14.html" />
   <id>tag:www.applistar.com,2007://1.437</id>
   
   <published>2008-12-07T07:29:12Z</published>
   <updated>2009-04-13T03:14:19Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="999TOP News" scheme="http://www.sixapart.com/ns/types#category" />
   
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<a href="http://www.robotken.com/"><img src="/images/news/jeziles.jpg"></a>
<a href="http://www.etrobo.jp/"><img src="/images/news/etrobo_banner.gif"></a>
<br>]]>
      <![CDATA[株式会社アプリスターは <a href="http://robotken.blog120.fc2.com/blog-entry-55.html"><span style="color: #3366ff">東京工芸大学ロボット研究会のサポーター企業 </span></a>になりました。<br>
全日本学生室内飛行ロボットコンテスト（飛行船タイプ）　初出場優勝！しました。
<br>
<strong><span style="color: #990000">おめでとうございます！！</span></strong>]]>
   </content>
</entry>
<entry>
   <title>DN7020K10</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2008/10/dn7020k10.html" />
   <id>tag:www.applistar.com,2008://1.448</id>
   
   <published>2008-10-30T00:40:03Z</published>
   <updated>2009-04-13T05:50:01Z</updated>
   
   <summary>
</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      DN7020k10 The DN7020k10 is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. A single DN7020k10 configured with 20 Altera Stratix 3SL340s can emulate up to 52 million gates of logic as measured by LSI. This product is also pin-compatible with Stratix IV, so it will be able to provide a cool 104 million gates when utilizing the 4SE680. All FPGA resources are available to the target application and any subset of FPGAs can be stuffed and each FPGA position can be stuffed with any available speed grade.

      <![CDATA[<img src="http://www.applistar.com/DN7020k10_bd_lvds_thumb.png" alt="DN7020k10_bd_lvds_thumb.png" width="544" />
<img src="http://www.applistar.com/DN7020k10_bd_se_thumb.png" alt="DN7020k10_bd_se_thumb.png" width="544" height="353" />
]]>
   </content>
</entry>
<entry>
   <title>DN7006K10PCIe-8T</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2008/04/dn7006k10pcie8t.html" />
   <id>tag:www.applistar.com,2008://1.442</id>
   
   <published>2008-04-11T05:27:41Z</published>
   <updated>2009-04-13T05:56:19Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      The DN7006k10PCIe-8T is a complete logic prototyping system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN7006k10PCIe-8T is hosted in an 8-lane PCIe bus (GEN1), but can also be used stand-alone and configured via USB and/or Compact FLASH. The board achieves high gate density and allows for fast target clock frequencies by utilizing the largest FPGA from Altera&apos;s Stratix3 family. Any subset of FPGA&apos;s can be stuffed and we can acommodate any combination of speed grades. 
      <![CDATA[<a href="http://www.applistar.com/images/DN7006K10PCIe-8T/DN7006K10PCIe-8T_bd_SS_v1_001.jpg">
<img src="http://www.applistar.com/images/DN7006K10PCIe-8T/DN7006K10PCIe-8T_bd_SS_v1_001_thumb.jpg" alt="" width="527" height="406" align="center" />
</a><br />
<p align="center">
Single-ended
</p>
<br />
<a href="http://www.applistar.com/images/DN7006K10PCIe-8T/DN7006K10PCIe-8T_bd_LVDS_v1_04.jpg">
<img src="http://www.applistar.com/images/DN7006K10PCIe-8T/DN7006K10PCIe-8T_bd_LVDS_v1_04_thumb.jpg" alt="" width="527" height="406" align="center" />
</a><br />
<p align="center">
LVDS
</p>
]]>
   </content>
</entry>
<entry>
   <title>MATLABパートナー企業になりました</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2008/02/matlab.html" />
   <id>tag:www.applistar.com,2008://1.441</id>
   
   <published>2008-02-29T07:26:22Z</published>
   <updated>2009-04-13T03:16:26Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="999TOP News" scheme="http://www.sixapart.com/ns/types#category" />
   
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<!--
<a href="http://www.cybernet.co.jp/matlab"><img alt="matlab.bmp" src="http://www.applistar.com/matlab.bmp" width="119" height="132" /></a><br>
-->]]>
      <![CDATA[株式会社アプリスターは<span style="color: #3366ff">MATLABパートナー企業</span>になりました。詳しくは、<a href="http://www.cybernet.co.jp/matlab/">こちら</a>をご覧下さい。
]]>
   </content>
</entry>
<entry>
   <title>EDS Fairに出展します</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2008/01/et2008.html" />
   <id>tag:www.applistar.com,2008://1.446</id>
   
   <published>2008-01-29T07:30:56Z</published>
   <updated>2009-04-13T03:13:15Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="999TOP News" scheme="http://www.sixapart.com/ns/types#category" />
   
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      株式会社アプリスターはEDS Fair 2009に出展します。
      <![CDATA[<p>
◇会&nbsp;&nbsp;&nbsp; 期&nbsp; 2009年1月22日(木),23日(金)　AM10:00～PM6:00<br />
◇出展場所&nbsp; パシフィコ横浜 ブースNo. 304
</p>
<p>
◇トピックス
</p>
<p>
&nbsp;○出展社セミナーの開催！
</p>
<p>
&nbsp;&nbsp; The DINI Group社とアルデック・ジャパン株式会社が共同で下記セミナーを行<br />
&nbsp;&nbsp; います。
</p>
<p>
&nbsp;&nbsp; ・日時：&nbsp;&nbsp; 1月22日（木） 15:30－16:15 会場： DM2<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1月23日（金） 13:30－14:15 会場： CM3
</p>
]]>
   </content>
</entry>
<entry>
   <title>DN9000K10</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2007/12/dn9000k10.html" />
   <id>tag:www.applistar.com,2007://1.438</id>
   
   <published>2007-12-27T01:00:00Z</published>
   <updated>2009-12-30T08:40:34Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<div style="color: #ff0000">NEW! VIRTEX-5!</div>
Logic emulation PWB based on the Xilinx Virtex 5&#8482; family of FPGA's using the FF1760 package. Designers can emulate up to <b>30 MILLION</b> ASIC gates on this product, which is hosted by USB and contains up to sixteen FPGAs. Easy configuration using CompactFlash cards.]]>
      <![CDATA[<a href="http://www.applistar.com/images/DN9000K10/DN9000K10block.png">
<img src="http://www.applistar.com/images/DN9000K10/DN9000K10block_thumb.png" alt="" align="center" />
</a>
]]>
   </content>
</entry>

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