<?xml version="1.0" encoding="UTF-8"?>
<feed xmlns="http://www.w3.org/2005/Atom">
   <title>アプリスター</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/" />
   <link rel="self" type="application/atom+xml" href="http://www.applistar.com/atom.xml" />
   <id>tag:www.applistar.com,2010://1</id>
   <updated>2010-06-23T00:17:18Z</updated>
   <subtitle>(株)アプリスターのWebサイト</subtitle>
   <generator uri="http://www.sixapart.com/movabletype/">Movable Type 3.33-ja</generator>

<entry>
   <title>DNDPB_S327</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/06/dndpb_s327.html" />
   <id>tag:www.applistar.com,2010://1.465</id>
   
   <published>2010-06-22T23:47:24Z</published>
   <updated>2010-06-23T00:17:18Z</updated>
   
   <summary>

</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      27 of the largest Altera Cyclone 3 FPGAs. Hosted via Ethernet. 
      <![CDATA[<a href="http://www.applistar.com/board_front6.html" onclick="window.open('http://www.applistar.com/board_front6.html','popup','width=1942,height=596,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/board_front6.jpg" width="510" alt="" /></a>]]>
   </content>
</entry>
<entry>
   <title>DN7406k10PCIe8T</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/06/dn7406k10pcie8t.html" />
   <id>tag:www.applistar.com,2010://1.464</id>
   
   <published>2010-06-22T23:36:04Z</published>
   <updated>2010-06-23T00:18:20Z</updated>
   
   <summary>

</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      The DN7406k10PCIe-8T is a complete logic prototyping system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN7406k10PCIe-8T achieves high gate density and allows for fast target clock frequencies by utilizing the largest FPGA from Altera&apos;s Stratix IV family. Any subset of FPGAs can be stuffed and we can accommodate any combination of speed grades in any FPGA position. 
      <![CDATA[<a href="http://www.applistar.com/7406k10pciefront.html" onclick="window.open('http://www.applistar.com/7406k10pciefront.html','popup','width=936,height=719,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/7406k10pciefront.jpg" width="510" alt="" /></a>]]>
   </content>
</entry>
<entry>
   <title>DN7002k10MEG</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/06/dn7002k10meg_1.html" />
   <id>tag:www.applistar.com,2010://1.463</id>
   
   <published>2010-06-22T23:09:16Z</published>
   <updated>2010-06-23T00:18:42Z</updated>
   
   <summary>

</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      The DN7002k10MEG is a complete logic emulation system that enables ASIC or IP designers to prototype system-on-a-chip (SOC) logic and memory designs for a fraction of the cost of existing solutions. It can be used stand-alone or hosted via a USB interface. A single DN7002k10MEG configured with two Altera Stratix III 3SL340s can emulate up to 5 million gates of logic as measured by LSI. This product is pin-compatible with the Stratix IV which will be coming in 2009 and will allow the board to emulate 10.5 million ASIC gates when configured with the 4SE820. Any subset of FPGAs can be stuffed and each FPGA position can be stuffed with any available speed grade. 
      <![CDATA[<a href="http://www.applistar.com/7002k10MEG_front.html" onclick="window.open('http://www.applistar.com/7002k10MEG_front.html','popup','width=1718,height=842,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/7002k10MEG_front.jpg" width="510" alt="" /></a>]]>
   </content>
</entry>
<entry>
   <title>DN2076k10</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/06/dn2076k10.html" />
   <id>tag:www.applistar.com,2010://1.462</id>
   
   <published>2010-06-14T04:00:29Z</published>
   <updated>2010-06-23T00:16:54Z</updated>
   
   <summary>



</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[7 of the largest Xilinx Virtex-6 FPGAs.  Up to 37 million gates of ASIC logic.</td>
]]>
      <![CDATA[<a href="http://www.applistar.com/DN2076K10_blckv1001.html" onclick="window.open('http://www.applistar.com/DN2076K10_blckv1001.html','popup','width=1650,height=1275,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DN2076K10_blckv100-thumb.png" width="510" height="394" alt="" /></a>]]>
   </content>
</entry>
<entry>
   <title>DNV6_F2_PCIe</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/06/dnv6_f2_pcie.html" />
   <id>tag:www.applistar.com,2010://1.461</id>
   
   <published>2010-06-14T00:53:49Z</published>
   <updated>2010-06-23T00:16:32Z</updated>
   
   <summary>

</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[ 2 of the largest Xilinx Virtex-6 FPGAs.  Up to 11 million gates of ASIC logic.  644 pins between FPGAs for easy logic partitioning.</td>
]]>
      <![CDATA[<a 
<img alt="DNV6_F2_PCIe_front_thumb1.jpg" src="http://www.applistar.com/DNV6_F2_PCIe_front_thumb1.jpg" width="510" alt="" /></a>]]>
   </content>
</entry>
<entry>
   <title></title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/05/post_18.html" />
   <id>tag:www.applistar.com,2010://1.460</id>
   
   <published>2010-05-24T05:36:07Z</published>
   <updated>2010-05-24T05:38:22Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="999TOP News" scheme="http://www.sixapart.com/ns/types#category" />
   
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[製品・サービスに関するお問い合わせはフォームから

<a href="http://at4.tactnet.co.jp/appli/inquiry/" target="_blank"><span style="font-size: medium; color: #3366ff"><strong>お問い合わせフォーム</strong></span></a>

お気軽にお問い合わせください]]>
      
   </content>
</entry>
<entry>
   <title>DNMEG_V5T_10G</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/01/dnmeg_v5t_10g.html" />
   <id>tag:www.applistar.com,2010://1.457</id>
   
   <published>2010-01-14T09:33:49Z</published>
   <updated>2010-06-23T00:15:50Z</updated>
   
   <summary>


</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      Meg-Array daughter card adds 10GbE (via SFP+) to any DINI Group FPGA base board.
      <![CDATA[<a href="http://www.applistar.com/DNMEG_V5T-10Gblk_v11.html" onclick="window.open('http://www.applistar.com/DNMEG_V5T-10Gblk_v11.html','popup','width=1650,height=1275,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DNMEG_V5T-10Gblk_v11-thumb.png" width="450"  alt="" /></a><img src="http://www.applistar.com/rohs.png"  width="80" alt="" />]]>
   </content>
</entry>
<entry>
   <title>DNV6F6PCIe</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/01/dnv6f6pcie.html" />
   <id>tag:www.applistar.com,2010://1.456</id>
   
   <published>2010-01-12T11:17:22Z</published>
   <updated>2010-06-23T00:15:31Z</updated>
   
   <summary>




</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[With 6 VIRTEX-6 FPGAs, the <b>DNV6F6PCIe</b> is a complete logic prototyping system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions.]]>
      <![CDATA[<a href="http://www.applistar.com/DNV6F6PCIe_blckv1111.html" onclick="window.open('http://www.applistar.com/DNV6F6PCIe_blckv1111.html','popup','width=1650,height=1275,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DNV6F6PCIe_blckv1111-thumb.png" width="510" alt="" /></a>]]>
   </content>
</entry>
<entry>
   <title>DNBFC_S12_PCIe</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2010/01/dnbfc_s12_pcie.html" />
   <id>tag:www.applistar.com,2010://1.455</id>
   
   <published>2010-01-12T10:15:40Z</published>
   <updated>2010-06-23T00:15:12Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      Algorithm Acceleration System. Twelve Xilinx Spartan-6 FPGAs in the FF484 package. 12 DDR3 SODIMMs (2Gb each). Dedicated PCIe, 4-lane controller (GEN1 or GEN2). Enhanced IP Security with AES and Device DNA protection.
      <![CDATA[<a href="http://www.applistar.com/DNBFC_S12_PCIe_blckv14.html" onclick="window.open('http://www.applistar.com/DNBFC_S12_PCIe_blckv14.html','popup','width=3300,height=2550,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DNBFC_S12_PCIe_blckv14-thumb.png" width="580" alt="" /></a>
<p style="top: -20px; left: -50px; position: relative;" align="right"><b><i>(Bigger, Faster, Cheaper)</i><br>Spartan-6 FPGA Algorithm Acceleration System<br>For High Performance Computing<br>12 Low-cost FPGAs with DDR3 memory<br>Hosted via 4-lane PCI Express (GEN1/GEN2)</b></p>
]]>
   </content>
</entry>
<entry>
   <title>DN-DualV6-PCIe-4</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/12/dndualv6pcie4.html" />
   <id>tag:www.applistar.com,2009://1.454</id>
   
   <published>2009-12-30T07:16:46Z</published>
   <updated>2010-06-23T00:14:47Z</updated>
   
   <summary>

</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      Two Xilinx Virtex-6 FPGAs in the FF1156 package. 2 DDR3 SODIMMs (up to 4GB each) Select any of the following FPGAs: SX475T,SX315T,LX365T,LX240T,LX195T,LX130T. Marvell MV78200 Dual CPU for massive date manipulation and movement.
      <![CDATA[<img alt="V6_LOGOr.PNG" src="http://www.applistar.com/V6_LOGOr.PNG" width="100"  /><a href="http://www.applistar.com/DN-DualV6-PCIe-4_BD_v210.html" onclick="window.open('http://www.applistar.com/DN-DualV6-PCIe-4_BD_v210.html','popup','width=5100,height=6600,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false"><img src="http://www.applistar.com/DN-DualV6-PCIe-4_BD_v210-thumb.png" width="450" alt="" /></a>
]]>
   </content>
</entry>
<entry>
   <title>DNDSP_40G</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/12/dndsp_40g.html" />
   <id>tag:www.applistar.com,2009://1.453</id>
   
   <published>2009-12-30T07:13:21Z</published>
   <updated>2010-06-14T03:57:58Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<p>
The DNDSP_40G is a circuit board that is plugged into any PCIe tower or server. Each board has four TMS320C6455 fixed-point digital signal processors, enabling massive fixed-point processing power to be applied to data-intensive applications independent of the host processor. Each DSP has a 128M x 32 DDR memory. Each DSP is connected to a Serial RapidIO (SRIO) Central packet Switch (IDT80KSW0005) with a 4x port. Each port is clocked at the maximum SRIO frequency supported by the CPS and DSP.
</p>
<p>
&nbsp;
</p>
]]>
      <![CDATA[<div align="center">
<span style="font-size: x-small; color: #0000ff">DNDSP_40G<br />
Quad-DSP Farm Cluster Element with Serial Rapid I/O Interconnect</span><a href="http://www.applistar.com/DNDSP_40G_blckv111.html" onclick="window.open('http://www.applistar.com/DNDSP_40G_blckv111.html','popup','width=3508,height=2479,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false">
<img src="http://www.applistar.com/DNDSP_40G_blckv11-thumb.png" alt="" width="550" height="388" />
</a>
</div>
]]>
   </content>
</entry>
<entry>
   <title>DN9200K10PCIe-8T</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/04/post_17.html" />
   <id>tag:www.applistar.com,2009://1.452</id>
   
   <published>2009-04-13T04:51:49Z</published>
   <updated>2010-06-14T04:00:06Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<p>
The DN9200k10PCIe-8T is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN9200k10PCIe-8T is hosted in an 8-lane PCIe slot or can be used stand-alone and configured via USB or Compact FLASH. A single board configured with 2 Xilinx Virtex-5 LX330&#39;s can emulate up to 4 million gates of logic as measured by LSI.
</p>
]]>
      <![CDATA[<a href="http://www.applistar.com/DN9200k10PCIe8T_blockd.html" onclick="window.open('http://www.applistar.com/DN9200k10PCIe8T_blockd.html','popup','width=1045,height=795,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false">
<img src="http://www.applistar.com/DN9200k10PCIe8T_blockd.png" alt="DN9200k10PCIe8T_blockd.png" width="550" />
</a>
]]>
   </content>
</entry>
<entry>
   <title>DN7002k10MEG</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2009/04/dn7002k10meg.html" />
   <id>tag:www.applistar.com,2009://1.450</id>
   
   <published>2009-04-13T00:45:03Z</published>
   <updated>2009-04-13T05:27:15Z</updated>
   
   <summary>
</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      The DN7002k10MEG is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype system-on-a-chip (SOC) logic and memory designs for a fraction of the cost of existing solutions. It can be used stand-alone or hosted via a USB interface. A single DN7002k10MEG configured with two Altera Stratix III 3SL340s can emulate up to 5 million gates of logic as measured by LSI. This product is pin-compatible with the Stratix IV which will be coming in 2009 and will allow the board to emulate 10.5 million ASIC gates when configured with the 4SE680. Any subset of FPGAs can be stuffed and each FPGA position can be stuffed with any available speed grade.

      <![CDATA[<img src="http://www.applistar.com/7002_bd_A.jpg" alt="7002_bd_A.jpg" width="550" />
<a href="http://www.applistar.com/7002_bd_B_thumb.html" onclick="window.open('http://www.applistar.com/7002_bd_B_thumb.html','popup','width=599,height=447,scrollbars=no,resizable=no,toolbar=no,directories=no,location=no,menubar=no,status=no,left=0,top=0'); return false">
<img src="http://www.applistar.com/7002_bd_B_thumb.jpg" alt="7002_bd_A.jpg" width="550" />
</a>
]]>
   </content>
</entry>
<entry>
   <title>ベトナムにIT子会社を設立</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2008/12/it.html" />
   <id>tag:www.applistar.com,2008://1.445</id>
   
   <published>2008-12-25T00:56:56Z</published>
   <updated>2009-12-29T23:15:31Z</updated>
   
   <summary></summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="999TOP News" scheme="http://www.sixapart.com/ns/types#category" />
   
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      <![CDATA[<p>
株式会社アプリスター　はASIC設計検証サービスやFPGA評価ボードを提供しています。平成２０年１０月にベトナムにIT子会社設立しました。オフショア開発による効率的な設計支援体制を提案しています。ベトナムのトップクラス大学出身者のエンジニアを御社の設計現場に派遣いたします。またiPhone, Android等の携帯アプリを開発いたします。
</p>
<p>
<a href="http://mobile.applistar.com/">http://mobile.applistar.com/</a>
</p>
]]>
      
   </content>
</entry>
<entry>
   <title>DN7020K10</title>
   <link rel="alternate" type="text/html" href="http://www.applistar.com/2008/10/dn7020k10.html" />
   <id>tag:www.applistar.com,2008://1.448</id>
   
   <published>2008-10-30T00:40:03Z</published>
   <updated>2009-04-13T05:50:01Z</updated>
   
   <summary>
</summary>
   <author>
      <name>applistar1</name>
      
   </author>
         <category term="010The DiNI Group" scheme="http://www.sixapart.com/ns/types#category" />
         <category term="020製品" scheme="http://www.sixapart.com/ns/types#category" />
   
   <category term="4" label="製品情報" scheme="http://www.sixapart.com/ns/types#tag" />
   
   <content type="html" xml:lang="ja" xml:base="http://www.applistar.com/">
      DN7020k10 The DN7020k10 is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. A single DN7020k10 configured with 20 Altera Stratix 3SL340s can emulate up to 52 million gates of logic as measured by LSI. This product is also pin-compatible with Stratix IV, so it will be able to provide a cool 104 million gates when utilizing the 4SE680. All FPGA resources are available to the target application and any subset of FPGAs can be stuffed and each FPGA position can be stuffed with any available speed grade.

      <![CDATA[<img src="http://www.applistar.com/DN7020k10_bd_lvds_thumb.png" alt="DN7020k10_bd_lvds_thumb.png" width="544" />
<img src="http://www.applistar.com/DN7020k10_bd_se_thumb.png" alt="DN7020k10_bd_se_thumb.png" width="544" height="353" />
]]>
   </content>
</entry>

</feed>
