製品

TCP Offload Engine IP – 128 Sessions (TOE128)

Features Description Pictures

  • FPGA TCP Offload Engine (TOE) IP for networking applications requiring minimum latency and deterministic latency
  • Supplied as encrypted .ngc (Xilinx) or optional verilog source
  • Integrated PCIe bridge (required) provided in encrypted .ngc format
  • Complete simulation models and text fixtures
  • Host CPU NOT involved in payload data transfer
    • 0% CPU load during middle of TCP session
    • TCP data packets handled by TOE not passed to CPU
  • Full 10GbE line rate
    • No Ethernet pause frames generated
  • CPU required only for High complexity/low importance network features:
    • Setup/teardown of TCP session
    • ARP, ping, DHCP, SMTP, et. al.
    • Linux driver with ‘C’ source included
  • Layers 2, 3, 4, 5 (datalink, network, transport, and session)
  • Layers 6, 7 (presentation , application) is user’s responsibility in FPGA
  • MTU of 1536 bytes
  • CRC validation and checksum validation
    • Ethernet CRC validation
    • IP and TCP checksum validation
  • Reordering of out-of-order packets
  • Nagle algorithm
  • Fast retransmit
  • Congestion avoidance
  • Packet retransmission upon error/lost/out of order packet reception
  • 128 TCP/IP session per instantiated TOE
  • Additional TOEs can be cascaded to support multiple sessions
    • Limited only by FPGA resources
  • Client or server mode
  • Configurable TX and RX replay buffer
    • 4KB -> 64KB
  • Protection Against Wrapped Sequences (PAWS)
  • Configurable port number
  • IPv4 with future upgrade paths to IPv6/IPng
    • TBD (consult factory)
  • TCP timestamps for congestion avoidance (optional)
  • Configurable timeouts
  • Targeted to the DINI Group boards:
  • Direct interface to the 10 Gigabit Ethernet Media Access Controller (10GEMAC) (required).
  • Tested also with the free 10G MAC from OpenCores
  • 64-bit bus interface:
    • Synchronous FIFO clocked at 156.25Mhz
    • Optional asynchronous FIFO interface with 4-6 clocks cycles of added latency
  • Optimized for lowest receive (about 13 clk cycles) AND transmit latency (about 15 clk cycles) at 156.25Mhz. (2 RX longer latency, 5 TX longer latency – roughly). With store&forward latency in each direction.
  • Does 128 TCP/IP sessions in a single module (each session is a connection to 1 other computer).
  • Takes less than 50% of the FPGA (410).
  • Xilinx or Altera versions available.
  • User selectable amount of internal FPGA ram for replaybuffers (4KBytes to 256KBytes).
  • Optional external memory (DRAM) for increased size retransmit buffers.
  • Can achieve >90% of the 10GBE bandwidth (in both transmit and receive) with a single module. Multiple modules can achieve 100% of the 10GBE bandwidth.
  • Multiple TOE128′s can be connected to the same ethernet if 128 sessions isn’t enough. Possibility of doing more than 128 sessions in a TOE128 – contact factory with your requirements.
  • Multiple TOE1 and TOE128 can be connected to the same ethernet.
  • Multiple sessions can be a server on the same port number (like a webserver), or different port numbers.
  • Good packetization controls from the user for TX data (i.e. you can control where the packet boundaries occur).
  • Single RX and TX bus to the user design (with N-to-1 multiport mux example for TX to make the bus interface simple for different requestors).
  • ZERO software overhead after setting up the connection information (IP and PORT numbers).
  • TCPIP setup (SYN) and teardown (FIN) all done in hardware.
  • RX packets not claimed by TOE128 get sent to the NIC.
  • 64KByte transmit buffer available on ALL session at the same time without using that much internal FPGA memory.
  • One TX session hogging too much memory, won’t stop the other sessions from making TX progress.
  • Each session can be on a different VLAN (if needed).
  • TX datapath has byte packer for ease of connection to your design.
  • RX early datapath available – if you can do something useful with the packet data before it’s been validated.
  • TCPIP Features:
    • retransmit
    • MSS/MTU
    • RTT/persist/replay timers
    • RX reordering (optional)
    • server and client mode supported on each concurrent TCPIP session
    • RFC793/791
    • upto 64KBytes per session for retransmit buffering
    • congestion control
    • RTO
  • FPGA resources required:
    • SLICES: assume about the same as TOE1 (approx 3% of V5-565).
    • RAMB36s: 28 to 105 depending on TX buffer size (3.5% to 13% of Kintex 410, or 3% to 12% of V6-565)
  • Netlist for toe128 and PCIE interface, verilog source for all other pieces
  • Entire TOE128 design runs at 156.25Mhz. Clock domain change FIFOs available for the user interface side so you can run it at a slower/faster frequency
  • Coming soon to a Dini board near you!
  • Other items coming soon (contact factory for details):
    • Dini 10GBE MAC low latency
    • 40GBE support
  • Related Documents