製品

DNS5GX_F2

Monster’s Evil Interior Decorator

ASIC Prototyping EngineDual Altera Stratix V FPGAs 16 million ASIC Gates

  • Cabled, PCIe-hosted logic prototyping system
    • 2 – Altera Stratix V FPGAs
      • 5SGXAB, A9, A7, A5 (largest to smallest)
        • for logic prototyping
      • 5SGSD8,D6
        • for signal processing
    • 100% FPGA resources available for user application
  • 16.6M+ ASIC gates (reasonable ASIC measure) with two 5SGXAB
    • 7,852 – 18×18 multipliers with dual 5SGSD8 (8M gates of logic)
  • 4 configurable high-speed serial interface card slots (IOB), 2 per FPGA
    • 12 serial links per slot clocked at 14.1 GHz
    • 32 general purpose I/O for out of band signaling (OOB)
    • Options interfaces include:
      • 100 GbE Ethernet (via CFP module)
      • 40 GbE Ethernet
      • Quad QSFP+
      • Octal SFP+
      • GEN1/GEN2 PCIe
      • USB3
      • SMAs
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 700 MHz LVDS chip-to-chip DDR with -2 speed grade (1.4 Gb/s)
    • Reference designs for integrated I/O pad shift registers
      • 10x FPGA to FPGA pin multiplexing per LVDS pair
      • Greatly simplified logic partitioning
      • Source synchronous clocking for LVDS
  • 2 separate DDR3 SODIMMs, PC3-8500
    • 64-bit data
    • Addressing/power to support 4GB
    • DDR3 Verilog reference design provided (no charge)
      • VHDL on special request
  • Marvell MV78200 Discovery Innovation Dual CPU
    • 1 GHz clock
    • Dual USB2.0 ports (Type B connector)
    • Dual Serial-ATA II connectors for 2 external hard drives (SATA II)
    • Gigabit Ethernet interface
      • 10/100/1000 GbE (RJ45 connector)
    • Sheeva™ CPU Core (ARM v5TE compliant)
      • Out-of-order execution
      • Single and double-precision IEEE compliant floating point
      • 16-bit Thumb instruction set increases code density
      • DSP instructions boosts performance for signal processing applications
      • MMU to support virtual memory features
      • Dual Cache: 32 KB for data and instruction, parity protected
      • L2 cache: 512 KB unified L2 cache per CPU (total of 1MB), ECC protected.
    • 1 GB external DDR2 SDRAM
      • Organized in a 128M x 64 configuration
      • 400 MHz (800 MHz data rate with DDR)
    • RS232 port for terminal-style observation
    • After configuration, both CPUs dedicated entirely to user application
    • Linux operating system
      • Source and examples provided via GPL license (no charge)
      • ~15 seconds to CPU boot
  • 3 board-level global clock networks (GCLK[2:0])
    • Separate programmable synthesizers for each network (Si5326)
      • Ultra-low jitter
      • 2 kHz – 710 MHz
      • User-configurable via USB, PCIe, et al.
    • Alternate clock sources:
      • Config FPGA
        • single-step
        • Divide
      • SMA for external clock insertion
    • 2 daughter card global clock networks
      • Allows insertion of global clock from daughter card
  • 2x 400-pin MEG-Array connectors for daughter card expansion
    • 180 signals
    • 700MHz on all signals with source synchronous LVDS
    • Reset, presence detect
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards with LVDS (up to 10x)
    • Hooks and models for other third-party partitioning solutions
  • Fast and Painless FPGA configuration
    • USB, PCIe, Ethernet et al.
    • Integrated sanity checks on configuration files
  • Custom base plate (standard) and optional rackmount chassis
    • Provides protection from those drooling engineers
  • Full support for embedded logic analyzers via JTAG interface
    • SignalTap and other third party debug tools
  • Convert MEG-Array expansion connectors to interconnect with the DNMEG_Intercon.
  • Enough status LEDs to function as a bathroom nightlight.