製品

DN2076k10

DN2076k10
Monster’s Refrigerator Repairman

ASIC Prototyping Engine Featuring Xilinx Virtex-6

  • Hosted via
    • 4-lane GEN1 PCIe (v1.1) via cable
    • SuperSpeed USB3.0/Hi-Speed USB2.0
    • 10/100/1000BASE-T Ethernet
    • Stand alone
  • Up to seven of the largest Xilinx Virtex-6 FPGAs
    • Six Xilinx Virtex-6 FPGAs (FF1760) from the following list:
      • LX760-2,-1,-1L(fastest to slowest)
      • LX550T-2,-1,-1L
    • One Xilinx Virtex-6T FPGA (FF1759) from the following list:
      • LX550T-2,-1,-1L (fastest to slowest)
      • SX475T-2,-1,-1L
      • SX315T-3,-2,-1,-1L
      • LX365T-3,-2,-1,-1L
      • LX240T-3,-2,-1,-1L
    • 50A VCCINT power per FPGA
  • 37+ million ASIC gates (ASIC measure) when stuffed with 6 Virtex-6 LX760 and 1 LX550T
  • 24, GTX low-powered transceivers:
    • 6.5 Gb/s with -3, -2 speed grade and 5.0 Gb/s with -1
    • Dual AMCC QT2225-2 Dual Port Serial 10Gbps-to-XAUI Transceivers
      • Four SFP+ sockets for any of the following interfaces:
        • 10 Gigabit Optical Ethernet
          • 10GBase-SR 10GBASE-LR 10GBASE-LRM 10GBase-ER
        • 10 Gigabit Copper Ethernet
          • 10GBASE-R direct attach
        • 10 Gigabit Sonet: 10GBase-LW
        • 10 Gigabit FibreChannel
    • SuperSpeed USB3.0
    • SFP socket
    • 4 channels using SMA connectors with LX550T/SX475T
      • 16 SMAs in total
    • 4-lane PCIe GEN1/GEN2 prototyping via iPASS cable
    • 2 SATA II ports: 1 host and 1 device
    • GTX Expansion header with LX550T/SX475T (SEARAY connector)
      • 8-lanes
  • FPGA to FPGA interconnect is LVDS
    • 1.3 Gb/s when using DDR with -2 speed grade
      • 1.0 Gb/s with -1 speed grade
    • LVDS pairs are length balanced and tested
    • LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
    • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • 52-pin Main Bus (MB[51:0]) connects all LX FPGAs
  • Auspy board interconnect models for logic partitioning assistance
  • Marvel MV78200 Discovery Innovation Dual CPU
    • 1 GHz clock
    • Dual USB2.0 ports (Type B connector)
    • Dual Serial-ATA II connectors for 2 external hard drives (SATA II)
    • Gigabit Ethernet interface
      • 10/100/1000 GbE (RJ45 connector)
    • Sheeva™ CPU Core (ARM v5TE compliant)
      • Out-of-order execution
      • Single and double-precision IEEE compliant floating point
      • 16-bit Thumb instruction set increases code density
      • DSP instructions boosts performance for signal processing applications
      • MMU to support virtual memory features
      • Dual Cache: 32 KB for data and instruction, parity protected
      • L2 cache: 512 KB unified L2 cache per CPU (total of 1MB), ECC protected.
    • 1 GB external DDR2 SDRAM
      • Organized in a 128M x 64 configuration
      • 400 MHz (800 MHz data rate with DDR)
    • RS232 port for terminal-style observation
    • After configuration, both CPUs dedicated entirely to user application
    • Linux operating system
      • Source and examples provided via GPL license (no charge)
      • ~15 seconds to CPU boot
  • 3 separate DDR3 SODIMMs, on FPGAs BDG
    • 533MHz, 1066 MB/s with -2 and -3 speed grades (PC3-8500)
      • 400 MHz, 800 Mb/s with -1 speed grade (PC3-6400)
    • 64-bit, with addressing/power to support 4GB in each socket
    • DDR3 Verilog/VHDL reference design provided (no charge)
    • DDR3 SODIMM data transfer rate: 68Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • SRAM: QDR, ASYNC, STD, or PSRAM, FLASH
      • DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2
      • Mictor, USB PHY, Extra Interconnect
  • Three independent low-skew global clock networks
    • G0, G1, G2
    • Three, high-resolution, user-programmable synthesizers for G0, G1, G2
      • Silicon Labs Si5326: 2kHz to 945 MHz
    • User configurable via Marvell uP RS232, USB, PCIe, or Ethernet
    • Global clocks networks distributed differentially and balanced
  • Add 8 SFP sockets to GTX Expansion Header
  • Flexible customization via daughter cards using expansion connector
    • 2 daughter card locations on FPGA A
    • 1 daughter card location on FPGA D
    • 400-pin FCI MEG-Array connector
      • Non proprietary, readily available, and cheap
    • 96 LVDS pairs + clocks (or 186 single-ended)
    • 650 MHz on all signals with source synchronous LVDS (-2 speed grade)
    • Signal voltage set by daughter card (+1.2V to +2.5V)
    • Reset
    • Supplied power rails (fused):
      • +12V (24W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using LVDS (up to 10x)
  • Fast and Painless FPGA configuration
    • USB, PCIe, Ethernet, JTAG
    • Stand-alone configuration with USB stick
    • Configuration Error reporting
    • Accelerated configuration readback for advanced debug
  • RS232 port for embedded FPGA-based SOC uP debug
    • Accessible from all FPGAs via separate 2-signal bus
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope and other third-party debug solutions
  • Status FPGA-controlled LEDs
    • Enough multicolored LEDs to function as a disco ball

Overview

The DN2076k10 is a complete logic prototyping system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN2076k10 is a stand-alone system and can be hosted by 4-lane PCIe cable (GEN1), USB or Ethernet. A single DN2076k10 configured with 6 Xilinx Virtex-6, LX760s and 1 LX550T can emulate up to 37 million gates of logic as measured by a reasonable ASIC gate counting standard. This gate count estimate number does not include embedded memories and multipliers resident in each FPGA. One hundred percent (100%) of the Virtex-6 FPGA resources are available to the user application. The DN2076k10 achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx's 40nm Virtex-6 family. Any subset of FPGAs can be stuffed and we can accommodate any combination of speed grades in any FPGA position.

Virtex-6 FPGAs from Xilinx

The DN2076k10 uses high I/O-count, 1759-pin and 1760-pin flip-chip BGA packages. The largest device, the LX760 in the FFG1760 package, has 1200 I/Os. All are utilized. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGAs. FPGA to FPGA busses are routed, tested, and characterized LVDS and run at 650MHz+ (which is 1.3 Gb/s when used in DDR mode and assumes -2 speed grade). Single-ended at the reduced speed of 225MHz is characterized and tested. Example designs utilizing the integrated I/O shift registers (ISERDES/OSERDES) with DDR for pin multiplexing are included. Each FPGA has a 50A VCCINT power supply.

A 52-pin Main Bus connects each of the six large FPGAs (MB[51..0]) to each other and the configuration FPGA (Config FPGA). The connection to the Config FPGA allows for data movement via USB, Ethernet, PCIe and SATA to any/all FPGAs via the Marvell MV78200 processor. 100% of the resources of the Virtex-6 FPGAs are dedicated to the user application.

Two possible Virtex-6 FPGAs can be stuffed in the A, B, C, D, E, and F positions. You are free to mix and match any FPGA with any available speed grade for each position from the following list (fastest to slowest):

  • LX760T-2,-1,-1L
  • LX550T-2,-1,-1L

Five possible Virtex-6 FPGAs can be stuffed in the G position. You are free to select a single FPGA in any speed grade from the following list (fastest to slowest):

  • LX550T-2,-1,-1L
  • SX475T-2,-1,-1L
  • SX315T-3,-2,-1,-1L
  • LX365T-3,-2,-1,-1L
  • LX240T-3,-2,-1,-1L

The maximum density stuffing option combines six LX760s with a single LX550T. When stuffed in this fashion, DN2076k10 is capable of prototyping >37 million gates of ASIC logic with plenty of resource margin. Of note is the SX475T, which contains a whopping 2,016, 25x18 multipliers per FPGA. With an SX475 stuffed in the G position, a mere 500k gates of emulation logic is lost, but a whopping 1152, 25x18 multipliers are gained. The SX475 is excellent at handling the DSP-heavy portions of your ASIC prototyping.

The Marvell MV78200 Discovery™ Dual CPU

A MONSTER for data movement and manipulation

Easy FPGA configuration is a required feature of large, multi-FPGA boards. We use an onboard CPU to handle this function. We chose a Marvell MV78200 from the Discovery™ Innovation CPU family. Bluntly stated, this CPU is massive, massive overkill for the mundane task of FPGA configuration. The MV78200 comes in a variety high performance interfaces, and all can be utilized to your advantage.

Dual Sheeva™ CPUs, 1GHz with floating point

And after we are done configuring the FPGAs we dedicate both CPUs to your application. The CPUs in the MV78200 are Marvell Sheeva™ cores, which are ARM v5TE compliant. The CPUs are clocked at 1GHz and each processor has a single and double precision floating point unit. A fixed 1 GB, DDR2 memory is standard and is useful for large amounts of high speed data buffering. The memory is organized as 128M x 64 and clocked at the full frequency allowed: 400MHz (800 MHz effective with DDR). This DDR2 bank is shared between the two CPUs. Boot code is resident in an SPI Flash, and application code is downloaded via any port: PCIe, USB, and Ethernet. We ship Linux as the standard operating system. Options exist for VxWorks and other real-time operating systems. Contact the factory for more information.

PCI Express

The Marvell 78200 acts as a two-port high-speed PCI Express switch (2.5Gbs). It connects all seven user FPGAs at 4-lane PCI Express speeds to a host computer. The Marvell 78200 has multiple DMA engines to pump data to and from any port. The user interface on the FPGA is a simple-to-use, pipelined A/D bus running at 6.4Gb/s. Drivers for data movement to and from a host machine are provided. A simple example FPGA design and host computer application streaming data at PCI Express x4 bandwidth to all seven FPGAs are provided.

Two Serial-ATA Ports (SATA II)

The MV78200 has two Serial-ATA Generation 2 (SATA II) ports, each capable of running at 3.0 Gb/s. SATA is intended for high speed data transfer to/from serial-ATA hard drives. Two SATA connectors are provided, allowing for direct, high-speed interfacing to external hard drives. The MV78200 has specialized enhanced DMA (EDMA) engines for HDD data transfer with 512-byte buffer for each channel. Examples of all possible data movement options, with source, are included.

GbE – 802.3 Gigabit Ethernet

The MV78200 can be controlled over it's built-in Ethernet port. The interface is a standard RJ45 connector. This port can be used to configure FPGAs, set board clocks and other resources, and access the Linux terminal. This terminal can also be used to send data to and from the user FPGA design at gigabit ethernet speeds.

Daughter cards for customization and expansion

Two 400-pin FCI MEG-Array connectors are attached to FPGA A and a single MEG-Array connector is attached FPGA D, enabling expansion for customization with daughter cards. This is a non-proprietary, industry standard connector and the mating connector is readily available. We can provide the mating connector to you at our cost. We are not fans of proprietary, hard-to-get, outrageously priced expansion connectors. The 192 signals (96 pairs) to/from each of these MEG-Array expansion connectors are routed differentially and can run at the limit of the Virtex-6 FPGA I/Os: 650 MHz (with -2 speed grade). Clocks, resets, and presence detection, along with abundant (fused) power are included in each connector.

Memory

Three separate DDR3 SODIMM sockets are connected to each FPGA B, D, and G. This style of SODIMM is 64-bits. Each socket is tested to 533MHz with a PC3-8500 DDR3 SODIMM. Standard, off-the-shelf DDR3 memory SODIMMs work fine and we can provide these for a small charge. The maximum memory size is probably 4GB per SODIMM socket in the short term. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes Flash, SSRAM, QDR SSRAM, mictors, USB PHYs, DDR2, RLDRAM I/II, and others. As always, reference material such as a DDR3 SDRAM controller is included (in Verilog, VHDL) at no additional cost.

Easy Configuration via PCIe, USB, or Ethernet

Configuration of the FPGAs is under the control of the Marvell CPU. Configuration data can be provided over PCI Express, USB, Ethernet, or on-board non-volatile memory. It can be copied to the board using a USB memory stick (provided). Configuration occurs automatically after the CPU boots. Sanity checks are performed automatically on the configuration files, streamlining the configuration process in the case of human error. Multiple LEDs provide instant status and operational feedback.

Status LEDs, Debug

As with all of our ASIC emulation boards, the DN2076k10 is loaded with LEDs. The LEDs are stuffed in several different colors (red, green, blue, orange et al.). We have found that if we put a working DN2076k10 on a rotating cord and hang it from the ceiling, the DN2076k10 can be used as a disco ball. When testing the disco feature, make sure an adult is present and wear eye protection. These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition to the party enhancing. A JTAG connector provides an interface to ChipScope and other third party debug tools.

Specs of FPGAs Available on the DN2076k10


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