製品

DN7020K10

Uncle of Monster
Altera Stratix IV ASIC Prototyping Engine

130 million ASIC gates

SE820 LVDS, for SE530 block diagram click here

  • USB2.0-hosted logic prototyping system with 2-20 Altera Stratix IV FPGAs
    • Stratix IV 4SE530 or 4SE820 in high I/O package (FF1760)
      • - 30A VCCINT power per FPGA
    • Backwards compatible with Stratix III, 3SL340
    • 100% FPGA resources available for user application
  • 130M+ ASIC gates (reasonable ASIC measure) with twenty 4SE820s
    • 82M+ ASIC gates with twenty Stratix IV 4SE530
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 600 MHz LVDS DDR chip-to-chip (1.2 Gb/s)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
      • 10x FPGA to FPGA pin multiplexing per LVDS pair
      • Greatly simplified logic partitioning
      • Source synchronous clocking for LVDS
  • Main Busses for global connectivity:
    • Main Bus A (MBUS48A), all FPGAs: 48 single-ended signals
    • Main Bus B (MBUS48B), all FPGAs: 48 single-ended signals
  • Auspy AES models for partitioning assistance
    • Hooks for other third-party partitioning solutions
  • 6 separate DDR2 SODIMMs (350MHz)
    • 64-bit data width, 350MHz operation
    • PC2-5300
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available:
      • QDR SSRAM, Mictor, RLDRAM I, RLDRAM II, SSRAM, DDR3, DDR1, IDC interconnect, SDRAM DRAM, FLASH, USB PHY, mobile SDRAM, and others
  • SODIMM Daughtercard expansion
  • 3 board-level global clock networks (GCLK[2:0])
    • Separate programmable synthesizers for each network (Si5326)
      • Ultra-low jitter (as low as 0.3 ps)
      • 2 kHz – 710 MHz
      • User configurable via Compact FLASH or USB
    • Alternate clock sources:
      • Config FPGA
        • single-step
        • divided
      • SMA for external clock insertion
  • 4 Daughter Card global clock networks (DC_GCLK[3:0]). Select from:
    • Clock from daughter card with PLL for zero-delay (ICS8745B-21)
      • DC_GCLK0: Select DC0 or DC3 as source
      • DC_GCLK1: Select DC2 or DC4 as source
      • DC_GCLK2: Select DC5 or DC7 as source
      • DC_GCLK3: Select DC1 or DC8 as source
    • SMA for external clock insertion
    • Selected FPGA outputs
      • DC_GCLK0: Select GCLK0 or FPGA1 as source
      • DC_GCLK1: Select GCLK1 or FPGA8 as source
      • DC_GCLK2: Select GCLK2 or FPGA13 as source
      • DC_GCLK3: Select FPGA14 or FPGA13 as source
  • 8, 400-pin MEG-Array connectors (FCI) for daughter card (DC) expansion
    • 190 single-ended on DC0,1,2,7
    • 47 LVDS pairs (FPGA -> DC), 48 LVDS pairs (DC -> FPGA) on DC[6:3]
      • Can be used as 190 single-ended signals
      • 600MHz on all signals with LVDS
      • Pin multiplexing to/from daughter cards using I/O shift registers (up to 10x)
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
  • Fast and Painless FPGA configuration
    • Compact FLASH, and/or USB
    • Integrated sanity checks on configuration files
    • Accelerated configuration readback
  • Custom base plate and 19" rackmount chassis
    • Provides protection from those drooling engineers
  • 4, RS232 ports for embedded uP debug
    • Accessible from all FPGAs
  • Full support for embedded logic analyzers via JTAG interface
    • SignalTap, and other third party tools
  • Convert a pair of MEG-Array expansion connectors to interconnect with the DNMEG_Intercon.
  • Enough status LEDs to adequately illuminate a Twisted Sister concert.