ASIC Prototyping Engine Featuring Xilinx Virtex-6
- Hosted via
- 4-lane GEN1 PCIe (v1.1) slot
- 10/100/1000BASE-T Ethernet
- Stand alone
- Six Xilinx Virtex-6 FPGAs (FF1759) from the following list:
- LX550T-2,-1,-1L (fastest to slowest)
- 30A VCCINT power per FPGA
- 24+ million ASIC gates (ASIC measure) when stuffed with 6 Virtex-6 LX550T
- 21+ million ASIC gates and 12,096, 25×18 multipliers with 6 Virtex-6 SX475T
- FPGA to FPGA interconnect is LVDS and GTX RocketI/O
- 710 MHz LVDS chip to chip with -3 speed grade (1.4 Gb/s with DDR)
- 650 MHz with -2 (1.3 Gb/s with DDR)
- 500 MHz with -1 (1.0 Gb/s with DDR)
- Pairs are length balanced and tested!
- LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz)
- Reference designs for integrated I/O pad ISERDES/OSERDES
- 10x pin multiplexing per LVDS pair
- Greatly simplified logic partitioning
- Source synchronous clocking for LVDS
- 710 MHz LVDS chip to chip with -3 speed grade (1.4 Gb/s with DDR)
- GTX Transceivers FPGA to FPGA
- 6.5 Gb/s with -3, -2 speed grade and 5.0 Gb/s with -1/-1L
- Data examples provided using Aurora protocol
- Bus connecting Config FPGA with each field FPGA
- 40 signals, single-ended (NMB[F..A])
- Full PCI Express throughput to user design
- Auspy board description models for logic partitioning assistance
- Marvel MV78200 Discovery Innovation Dual CPU
- 1 GHz clock
- Dual USB2.0 ports (Type B connector)
- Dual Serial-ATA II connectors (SATA II)
- Gigabit Ethernet interface
- 10/100/1000 GbE (RJ45 connector)
- Sheeva™ CPU Core (ARM v5TE compliant)
- Out-of-order execution
- Single and double-precision IEEE compliant floating point
- 16-bit Thumb instruction set increases code density
- DSP instructions boosts performance for signal processing applications
- MMU to support virtual memory features
- Dual Cache: 32 KB for data and instruction, parity protected
- L2 cache: 512 KB unified L2 cache per CPU (total of 1MB), ECC protected.
- 1 GB external DDR2 SDRAM
- Organized in a 128M x 64 configuration
- 400 MHz (800 MHz data rate with DDR)
- RS232 port for terminal-style observation
- After configuration, both CPUs dedicated entirely to user application
- Linux operating system
- Source and examples provided via GPL license (no charge)
- ~15 seconds to CPU boot
- 4 separate DDR3 SODIMMs, one for each corner Virtex-6 FPGA (ACFD)
- 533MHz, 1066 Mb/s with -2 and -3 speed grades (PC3-8500)
- 400 MHz, 800 Mb/s with -1 speed grade (PC3-6400)
- 64-bit, with addressing/power to support 4GB in each socket
- DDR3 Verilog/VHDL reference design provided (no charge)
- DDR3 SODIMM data transfer rate: 68Gb/s
- Alternate pin compatible memory cards available (consult factory for availability):
- SRAM: QDR, ASYNC, STD, or PSRAM, Flash
- DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2
- Mictor, USB PHY, Extra Interconnect
- 533MHz, 1066 Mb/s with -2 and -3 speed grades (PC3-8500)
- Three independent low-skew global clock networks
- G0, G1, G2
- Three, high-resolution, user-programmable synthesizers for G0, G1, G2
- Silicon Labs Si5326: 2kHz to 945 MHz
- User configurable via Marvell uP RS232, USB, PCI Express or Ethernet
- Global clocks networks distributed differentially and balanced
- Add 8 SFP sockets to GTX Expansion Header
- Flexible customization via daughter cards using expansion connector
- Daughter card location on FPGA D,E,F
- 400-pin FCI MEG-Array connector
- Non proprietary, readily available, and cheap
- 93 LVDS pairs + clocks (or 186 single-ended)
- 710 MHz (1.4 Gb/s) on all signals with source synchronous LVDS (assuming -3 speed grade)
- Signal voltage set by daughter card (+1.2V to +2.5V)
- Supplied power rails (fused):
- +12V (24W max)
- +3.3V (10W max)
- Pin multiplexing to/from daughter cards using LVDS (up to 10x)
- High Speed expansion via GTX connector
- Connector for each FPGA A, C, D
- 8 GTX lanes per connector
- 6.5 Gb/s per lane, each direction with -3 and -2 speed grade
- 5.0 Gb/s with -1 and -1L speed grade
- Fast and Painless FPGA configuration
- USB, PCIe, Ethernet, JTAG
- Stand-alone configuration with USB stick or on-board NAND Flash
- Configuration Error reporting
- Accelerated configuration readback for advanced debug
- RS232 port for embedded FPGA-based SOC uP debug
- Accessible from all FPGAs via separate 2-signal bus
- Full support for embedded logic analyzers via JTAG interface
- ChipScope and other third-party debug solutions
- Status FPGA-controlled LEDs
- Enough illumination to act as automobile fog lights
The DNV6F6PCIe is a complete logic prototyping system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. The DNV6F6PCIe is hosted in a 4-lane PCI Express bus (GEN1), but can be used stand-alone and configured via USB or Ethernet. A single DNV6F6PCIe configured with 6 Xilinx Virtex-6, LX550Ts can emulate up to 24 million gates of logic as measured by a reasonable ASIC gate counting standard. This gate count estimate number does not include embedded memories and multipliers resident in each FPGA. One hundred percent (100%) of the Virtex-6 FPGA resources are available to the user application. The DNV6F6PCIe achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx’s 40nm Virtex-6 family. Any subset of FPGAs can be stuffed and we can accommodate any combination of speed grades in any FPGA position.
Virtex-6 FPGAs from Xilinx
The DNV6F6PCIe uses high I/O-count, 1759-pin, flip-chip BGA packages. The larger devices (LX550T, SX475T) have 840 I/Os and 36 high-speed serial GTXs. The smaller devices (SX315T, LX365T, LX240T) have 720 I/Os and 24 GTXs. The FPGA to FPGA interconnect functionality gracefully degrades when utilizing the smaller devices.
Abundant fixed interconnects (either differential or single-ended) are provided between the FPGAs. FPGA to FPGA busses are routed, tested, and characterized LVDS and run at 710MHz+ (which is 1.4 Gb/s when used in DDR mode and assumes -3 speed grade). Single-ended at the reduced speed of 225MHz is characterized and tested. Example designs utilizing the integrated I/O shift registers (ISERDES/OSERDES) with DDR for pin multiplexing are included. FPGA to FPGA, GTP links are tested and characterized at 6.5 Gb/s (with -3/-2 speed grade) each direction. Data transfer examples using the Xilinx Aurora protocol are provided (with source). Each FPGA has its own 30A VCCINT power supply.
Six 40-pin busses (NMB[F..A]) are connected from the configuration FPGA (Config FPGA) to each field FPGA (ABCDEF). The connection to the Config FPGA allows for data movement via USB, Ethernet, PCI Express and SATA to any/all FPGAs. 100% of the resources of the field Virtex-6 FPGAs is dedicated to the user application.
Five possible Virtex-6 FPGAs can be stuffed in the A, B, C, D, E, and F positions. You are free to mix and match any FPGA with any available speed grade for each position from the following list (fastest to slowest): LX550T-2,-1,-1L, SX475T-2,-1,-1L, SX315T-3,-2,-1,-1L, LX365T-3,-2,-1,-1L, LX240T-3,-2,-1,-1L.
When stuffed with six LX550Ts, the DNV6FCPCIe is capable of prototyping >24 million gates of ASIC logic with plenty of resource margin. Of note is the SX475T, which contains a whopping 2,016, multipliers, each 25×18, per FPGA. When stuffed with six SX475Ts, the DNV6F6PCIe contains 12,096 multipliers in addition to more than 21 million gates of ASIC logic, making this product ideal for heavy DSP-based algorithmic acceleration and High Performance Computing (HPC) applications.
The Marvell MV78200 Discovery™ Dual CPU
A MONSTER for data movement and manipulation
Easy FPGA configuration is a required feature of large, multi-FPGA boards. We use an on-board Marvell MV78200 CPU from the Discovery™ Innovation CPU family. Bluntly stated, this CPU is massive, massive overkill for the mundane task of FPGA configuration. The MV78200 comes in a variety of high performance interfaces, and all can be utilized to your advantage.
Dual Sheeva™ CPUs, 1GHz with floating point
First and foremost are dual CPUs. And after we are done configuring the FPGAs we dedicate both CPUs to your application. The CPUs in the MV78200 are Marvell Sheeva™ cores, which are ARM v5TE compliant. The CPUs are clocked at 1GHz and each processor has a single and double precision floating point unit. A fixed 1 GB, DDR2 memory is standard and is useful for large amounts of high speed data buffering. The memory is organized as 128M x 64 and clocked at the full frequency allowed: 400MHz (800 MHz effective with DDR). This DDR2 bank is shared between the two CPUs. Boot code is resident in an SPI Flash, and application code is downloaded via any port: PCIe, USB, and Ethernet. We ship Linux as the standard operating system. Options exist for VxWorks and other real-time operating systems. Contact the factory for more information.
The Marvell 78200 acts as a two-port high-speed PCI Express switch (2.5Gbs). It connects all six user FPGAs at 4-lane PCI Express speeds to a host computer. The Marvell 78200 has multiple DMA engines to pump data to and from any port. The user interface on the FPGA is a simple-to-use, pipelined A/D bus running at 6.4Gb/s. Drivers for data movement to and from a host machine are provided. A simple example FPGA design and host computer application streaming data at PCI Express x4 bandwidth to all seven FPGAs are provided.
Two Serial-ATA Ports (SATA II)
The MV78200 has two Serial-ATA Generation 2 (SATA II) ports, each capable of running at 3.0 Gb/s. SATA is intended for high speed data transfer to/from serial-ATA hard drives. Two SATA connectors are provided, allowing for direct, high-speed interfacing to external hard drives. The MV78200 has specialized enhanced DMA (EDMA) engines for HDD data transfer with 512-byte buffer for each channel. Examples of all possible data movement options, with source, are included.
GbE – 802.3 Gigabit Ethernet
The MV78200 can be controlled over it’s built-in Ethernet port. The interface is a standard RJ45 connector. This port can be used to configure FPGAs, set board clocks and other resources, and access the Linux terminal. This terminal can also be used to send data to and from the user FPGA design at gigabit ethernet speeds.
Daughter cards for customization and expansion
A 400-pin FCI MEG-Array connector is attached to FPGA D, E, and F, allowing for customization with daughter cards. This is a non-proprietary, industry standard connector and the mating connector is readily available. We can provide the mating connector to you at our cost. We are not fans of proprietary, hard-to-get, outrageously priced expansion connectors. The 192 signals (96 pairs) to/from these MEG-Array expansion connectors are routed differentially and can run at the limit of the Virtex-6 FPGA I/Os: 710 MHz (with -3 speed grade). Clocks, resets, and presence detection, along with abundant (fused) power are included in each connector.
Four separate DDR3 SODIMM sockets are connected to each FPGA A, C, D, F. This style of SODIMM is 64-bits. Each socket is tested to 533MHz with a PC3-8500 DDR3 SODIMM. Standard, off-the-shelf DDR3 memory SODIMMs work fine and we can provide these for a small charge. The maximum memory size is probably 4GB per SODIMM socket in the short term. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, mictors, USB PHYs, DDR2, RLDRAM, and others. As always, reference material such as a DDR3 SDRAM controller is included (in Verilog, VHDL) at no additional cost.
Easy Configuration via PCIe, USB, or Ethernet
If the DNV6F6PCIe is hosted via PCIe, USB, or Ethernet, FPGA configuration occurs via the host under the control of one of the Marvell CPUs. If the board is used standalone, the FPGA configuration files are copied onto a USB stick and FPGA configuration occurs at power up after the Marvell processors have booted (~15 seconds or so). Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process in the case of errors. Multiple LEDs provide instant status and operational feedback.
Status LEDs, Debug
During a particularly heavy instance of Tule fog in Fresno, California, we have determined that the dozens of status LEDs are bright enough to act as automobile fog lights. Please don’t try this at home since the Tule fog is dangerous and quite depressing. When testing this fog-headlight feature, make sure an adult is present and wear eye protection. These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition fog illumination. A JTAG connector provides an interface to ChipScope and other third party debug tools.
Specs of FPGAs Available on the DNV6F6PCIe
- Product Brief [HiRes]
- Product Brief [LoRes]
- Board Errata
- Block Diagram
- V6 FPGA Production Errata
- Emu Software
- Emu Manual
- Marvell 78200 HW Specifications
- Marvell 78200 Functional Specs
- Virtex6 Overview
- Virtex6 Product Table
- PCIe DMA User Manual
- Dini Buses User FPGA Design Manual
- PCIe DMA (ConfigFPGA design) User Manual