製品

DN9200K10PCIe-8T

DN9200K10PCIe-8T
8-lane PCI Express ASIC Prototyping Board with Virtex-5 FPGAs

  • PCIe controller using Xilinx Virtex-5 LX50T FPGA
    • 8-lane PCIe (using GTPs)
      • 2.5 Gb/s per lane with Virtex-5 LXT (GEN1)
      • 5.0 Gb/s per lane with Virtex-5 FXT (GEN2)
    • Multiple options for PCIe controller
      • User supplied (for ASIC and SOC prototyping)
      • Fixed target/master (shipped with board)
      • Configuration via dedicated Flash, Compact Flash, or USB
  • One or two Xilinx Virtex-5 FPGAs
    • LX110, LX155, LX220, or LX330 (FF1760)
    • 100% FPGA resources available for user application
    • Nearly 4 million ASIC gates (LSI measure) with two LX330
      • Another 276k gates in LX50T
      • 443,520 Flip Flops with 2 LX330s and 1 LX50T
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 450Mhz LVDS chip to chip (900mb/s)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
      • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Main Bus (MB) — 36 signals
    • Single-ended
    • Connects to both V5 FPGAs and Spartan Configuration FPGA
  • Two DDR2 SODIMM (250MHz)
    • 64-bit data width, 200MHz operation
    • PC2-4200
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor, DDR3, interconnect
  • 3 board-level global clock networks (GCLK0, GCLK1, GCLK2)
    • Separate programmable synthesizers (Si5326) for each network
      • User-configurable via Compact Flash, USB, or PCI Express
    • Global clocks networks distributed differentially and balanced
    • Single-step clocking available
  • Flexible customization via daughter cards
    • Three, 400-pin MEG-Array connectors (FCI)
      • Two connectors on bottom and one on top
    • 93 LVDS pairs + clocks (or 186 single-ended) assuming LX330
    • 450MHz on all signals with LVDS
    • Signal voltage set by daughter card
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)
    • Convert MEG-Array connectors to FPGA interconnect with 
  • Fast and painless FPGA configuration
    • CompactFlash, PCI Express, USB, or JTAG
    • Integrated sanity checks on configuration files
    • Accelerated configuration readback
  • Full support for embedded logic analyzers via JTAG interface
  • 48 user-controlled status LEDs
    • 24 connected to FPGA A
    • 24 connected to FPGA B
    • enough illumination to perform cosmetic hair removal
  • Now 100% RoHS!
  • Emulate PCIe bridges with DNMEG V5T PCIe
  • The reDNPCIe_CBL commended accessory allows for use of the board outside of a PC chassis
  • Easy PCIe core prototyping with our exclusive PCIe PIPE Slowdown core