製品

DN9000K10PCI

DN9000K10PCI
Xilinx Virtex-5 Based ASIC Prototyping Engine

  • PCI-hosted logic prototyping system with 2-6 Xilinx Virtex-5 FPGAs
    • LX110, LX155, LX220, or LX330 (FF1760)
  • 100% FPGA resources available for user application
  • Nearly 12M ASIC gates (LSI measure) with 6 LX330s
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 400Mhz LVDS (800Mb/s) chip to chip
    • Reference designs for integrated I/O pad ISERDES/OSERDES
      • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Main Bus (MB) connects all FPGAs (169 signals)
    • Single-ended
  • 6 separate DDR2 SODIMMs (200MHz)
    • 1 SODIMM for FPGAs A,B,F,D
    • 2 SODIMMs for FPGAs C
    • 64-bit data width, 200MHz operation
    • PC2-3200/PC2-4200
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 25.6Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
  • Seven board-level global clock networks (GCLK0, GCLK1, GCLK2)
    • Three separate programmable synthesizers
      • User-configurable via CompactFlash or USB
    • Global clocks networks distributed differentially and balanced
    • Two single-step clocks
    • Three external differential clock inputs
  • Flexible customization via daughter cards
    • Three 400-pin Meg-Array connectors (FCI)
      • FPGAs D,E,F
      • 93 LVDS pairs + clocks (or 186 single-ended)
    • 400MHz on all signals with LVDS
    • Signal voltage set by daughter card
    • Reset
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)
  • Fast and Painless FPGA configuration
    • Compact Flash, PCI, JTAG, and/or USB
    • Integrated sanity checks on configuration files
    • Accelerated configuration readback
  • RS232 port for embedded uP debug
    • Accessible from all FPGAs
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro
  • Enough status LEDs to blind a large crash of rhinoceroses
  • Convert MEG Array expansion connectors to interconnect with the DNMEG_Intercon. Add 186 single-ended OR 93 pairs LVDS:
    • (FPGA D to E) OR (FPGA E to F)