DN6000k10Se

DN6000k10Se
VirtexII™-Pro Based
PCI Express-hosted ASIC Prototyping Engine
(1-lane and 8-lane versions)

Tested and Verified with IP from ASIC Architect
PCI Express PCI-SIG Compliant

(Standard configuration in blue)
(Optional in red)

PCIe-based PWB (1-lane or 8-lane)
Single VirtexII-Pro (or Pro X) FPGA in FF1704
- 2vp70 -5,-6,-7
- 2vp100 -5,-6
Four external independent SSRAMs
- 512k/1M/2M x 36
- pipeline or flowthrough
- ZBT or non-ZBT
Four independent DDR SDRAM banks
- 4 banks 32M x 16 (256MB)
- Options to 64M x 16 (512MB)
Two independent external FLASH memories
- 4M x 16
10 High Speed serial ports
- 2 GbE Fiber (4 MGTs) (requires -6 speed grade)
- 2 HSSDC2 – Infiniband (2 MGTs)
- 2 SATA (2 MGTs)
- 4 SMA (4 MGT)
One 200-pin high-speed connectors for awesome signal integrity
- custom daughter cards
- observation daughter cards (such as DN3k10SD or DNPMC104)
162 signals for observation/debug
- Fully compatible with the DN3k10SD
Onboard Power Supplies
- 5A onboard linear regulator for +1.5V
- 5A onboard switcher for +2.5V and Vtt
Two PowerPC 405 Cores
- Embedded 300+ MHz Harvard Architecture
- Hardware Multiply/Divide Unit
- Thirty-Two 32-bit General Purpose Registers
- 16 KB 2-Way Set-Associative Instruction Cache
- 16 KB 2-Way Set-Associative Data Cache
- Memory Management Unit (MMU)
- Timer Facilities
- Two dedicated external JTAG connectors for uP trace/debug
Three RS232 ports for PowerPC processor visibility
- 2 Tx/Rx
- 1 Tx only
Standalone operation via separate power connector
- +3.3V not needed on backplane
Fast/Easy FPGA configuration via standard SmartMedia FLASH card
- Microprocessor controlled (Atmega128L)
- RS232 port for configuration/operational status and control
- Fastest possible configuration using SelectMap parallel
  - 2vp70 configures in 1 second
- Sanity checking programs for bit files eases configuration hassles
6 low skew clocks distributed to FPGAs and test connector:
- 2 CY7B994 RoboClockII PLLs for the best clock distribution
- 1 FCT3805 low-skew clock driver (non-PLL)
- 2 user-selectable socketed oscillators
- PCI/PCI-X clock
- 1 dividable clock via CPLD
Boatloads of reference stuff included (FREE)
- SDRAM controller (Verilog/VHDL)
- DDR SDRAM controller (Verilog/VHDL)
- PowerPC ‘Hello World’
- UARTs
- DOS-based utilities
- Board test(s)
- PCI Drivers (with C code)
  - Windows XP, ME, 2000, 98, NT
  - LINUX, Solaris
Full support for embedded logic analyzers
- ChipScope, ChipScope PRO
- Identify™ from Synplicity

Overview

The DN6000K10Se is a complete logic emulation system that enables ASIC or IP designers to prototype logic, memory, and embedded systems designs for a fraction of the cost of other solutions. The DN6000K10Se is hosted in 1-lane or 8-lane PCI Express slot, or can be used standalone. A DN6000K10Se can emulate up to 600,000 gates of logic as measured by LSI. In addition, the VirtexII Pro FPGA contains two 300MHz+ 405 PowerPC microprocessors, 328-556 18×18 multipliers, and more than 438 Kbytes of block RAM memory. Ten serial RocketI/O ports are provided on the top of the circuit board and can support a variety of serial communication protocols at speeds up to 3.125 GB/s (with -6, -7 speed grade). The DN6000K10Se is designed for performance – all external memories run at a frequency of at least 133MHz and the FPGA internal speed is limited only by the logic within. A high I/O count, 1704-pin BGA package is employed allowing for a host of external interface features including test signals, four SSRAMs, four DDR SDRAMs, and two FLASHs. A total of 162 signals are provided via a 200-pin connector on the top of the PWB for logic analyzer-based debugging, or for pattern generator stimulus. Custom daughter cards can be mounted to this connector to interface the DN6000K10Se to application-specific circuits.

Easy Configuration Via SmartMedia

The configuration bit file for the FPGA is copied onto a 32/64/128-megabyte SmartMedia FLASH card (provided) and an on-board microprocessor controls the FPGA configuration process. An RS232 port provides detailed information regarding the configuration process, completely bypassing time-consuming debugging of the configuration process. FPGA configuration occurs at close to the fastest possible parallel frequency –48MHz. Eight LEDs provide instant status and operational feedback. Two of these LEDs are connected to the CPLD and can be user-configured.