- Stratix-3 3SL340-4, -3, -2 in high I/O package (FF1760)
- 100% FPGA resources available for user application
- Fully compatible with Stratix IV when available:
- 4SE680/4SE530 (FF1760)
- 10.5M+ ASIC gates with two Stratix IV 4SE680s
- 600MHz LVDS DDR chip-to-chip (1.2 Gb/s)
- Characterized and tested
- Reference designs for integrated I/O pad shift registers
- 10x FPGA to FPGA pin multiplexing per LVDS pair
- Greatly simplified logic partitioning
- Source synchronous clocking for LVDS
- Hooks for other third-party partitioning solutions
- 64-bit data width, 350MHz operation
- PC2-5300
- Addressing/power to support 4GB in each socket
- DDR2 Verilog/VHDL reference design provided (no charge)
- DDR2 SODIMM data transfer rate: 45 Gb/s
- Alternate pin compatible memory cards available:
- Matched length and differentially distributed to each FPGA
- Separate programmable synthesizers for each network (Si5326)
- Ultra-low jitter (as low as 0.3 ps)
- 2 kHz - 710 MHz
- User configurable via Compact FLASH or USB
- Alternate clock sources:
- Configuration FPGA for generation of single-step or dividend clock
- SMA for external clock insertion
- 1,116 total single-ended signals for daughter card expansion
- 47/46 LVDS pairs (FPGA -> DC), 46/47 LVDS pairs (DC -> FPGA)
- Can be used as 186 single-ended signals per connector
- 600 MHz (1.2Gb/s)
- Pin multiplexing to/from daughter cards using I/O shift registers (up to 10x)
- Supplied power rails (fused):
- +12V (24W max)
- +5V (10W max)
- +3.3V (10W max)
- Compact FLASH and/or USB
- Integrated sanity checks on configuration files
- Accelerated configuration readback
- Accessible from both FPGAs
- SignalTap and other third party tools
The DN7002k10MEG is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype system-on-a-chip (SOC) logic and memory designs for a fraction of the cost of existing solutions. The DN7002k10MEG is stand-alone or hosted via a USB interface. A single DN7002k10MEG configured with 2 Altera Stratix 3 3SL340s can emulate up to 5 million gates of logic as measured by LSI. This product is pin-compatible with the Stratix IV, so in 2009 we will be able to provide a cool 10.5 million ASIC gates by utilizing the 4SE680. This ASIC gate estimate does not include the embedded memories and multipliers resident in each FPGA. The DN7002k10MEG achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Altera's Stratix 3 (or 4) FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGAs can be stuffed and each FPGA position can be stuffed with any available speed grade.
Stratix 3 FPGAs from Altera
High I/O-count, 1760-pin, flip-chip BGA packages are utilized. Each FPGA has a total of 1120 I/O's. Abundant interconnects are provided between FPGAs. All pins of all banks of each FPGA are utilized. Where appropriate, FPGA to FPGA busses are routed and tested unidirectional LVDS, run at 600MHz+ (1.2Gb/s) but can be used single-ended at a reduced speed. Example designs utilizing the integrated I/O block shift registers with DDR (double data rate) for pin multiplexing are included. A separtate 72-pin main bus is connected to both FPGAs and an off-board connector. Thirty-six of these main bus signals are routed to the configuration FPGA.
Daughter cards
The DN7002k10MEG is easily adaptable to all applications via daughter cards. Six separate 400-pin FCI MEG-Array connectors allow for customization via expansion. Signals to/from these cards are routed differentially where appropriate and can run at the limit of the FPGA: 600MHz. Clocks, resets, and abundant (fused) power are included in each connector. Signals are routed from the FPGAs on a bank basis, and the daughter card selects the I/O voltage of the connector by driving the VccI/O of the FPGA bank. The I/O voltage ranges are +1.5V to +3.3V. The DNMEG_Intercon card can be used to convert Daughter A2 and B2 to add FPGA to FPGA interconnect.
Memory
A DDR2 SODIMM socket is connected to each FPGA. Each socket is tested to 350MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMMs (PC2-5300) work nicely and we can provide these for a small charge. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, RLDRAM I/II, SDR SDRAM, mictors, DDR1, DDR3, and others.
Easy Configuration via Compact Flash or USB
The configuration bit files for the FPgAs are copied onto a 128-megabyte Compact FLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Fully stuffed, the DN7002k10MEG configures in less than 10 seconds. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files streamlining the configuration process. Multiple LEDs provide instant status and operational feedback.
Laboratory testing is showing that the amount of light provided by the LEDs is enough to function as traffic signals.
As always, reference material such as DDR2 SDRAM controllers, flash controllers, et al. is included (in Verilog, VHDL, C) at no additional cost.
