DN7020K10
- USB2.0-hosted logic prototyping system with 2-20 Altera Stratix III FPGA's
- 3SL340-4, -3, or -2 in high I/O package (FF1760)
- 100% FPGA resources available for user application
- Fully compatible with Stratix IV when available.
- 52M+ ASIC gates (LSI measure) with twenty (20!) 3SL340s
- 104M+ ASIC gates with 20 Stratix IV 4SE680
- PCIe hosting with DNMEG_V5T_PCIe
- FPGA to FPGA interconnect is single-ended or LVDS
- 600 MHz differential chip-to-chip DDR (1.2Gb/s)
- Reference designs for integrated I/O pad shift registers
- 10x FPGA to FPGA pin multiplexing per LVDS pair
- Greatly simplified logic partitioning
- Source synchronous clocking for LVDS
- Main Busses for global connectivity:
- Main Bus A (MBUS48A), Main Bus B (MBUS48B)
- Auspy AES models for partitioning assistance
- Hooks for other third-party partitioning solutions
- 6 separate DDR2 SODIMMs (250MHz)
- 64-bit data width, 350MHz operation
- PC2-5300
- Addressing/power to support 4GB in each socket
- DDR2 Verilog/VHDL reference design provided (no charge)
- DDR2 SODIMM data transfer rate: 45Gb/s
- Alternate pin compatible memory cards available:
- QDR SSRAM, Mictor, RLDRAM I, RLDRAM II
- SSRAM, DDR3, DDR1, IDC interconnect, SDRAM DRAM
- FLASH, USB PHY, mobile SDRAM, and others
- 3 board-level global clock networks (GCLK[2:0])
- Separate programmable synthesizers for each network (Si5326)
- Ultra-low jitter (as low as 0.3 ps)
- 2 kHz-710 MHz
- User configurable via CompactFlash or USB
- Alternate clock sources:
- Configuration FPGA for generation of single-step or divided clock
- SMA for external clock insertion
- 4 Daughter Card global clock networks (DC_GCLK[3:0]). Select from:
- Clock from daughter card with PLL for zero-delay (ICS8745B-21)
- DC_GCLK0: Select DC0 or DC3 as source
- DC_GCLK1: Select DC2 or DC4 as source
- DC_GCLK2: Select DC5 or DC7 as source
- DC_GCLK3: Select DC1 or DC8 as source
- SMA for external clock insertion
- Selected FPGA outputs
- DC_GCLK0: Select GCLK0 or FPGA1 as source
- DC_GCLK1: Select GCLK1 or FPGA8 as source
- DC_GCLK2: Select GCLK2 or FPGA13 as source
- DC_GCLK3: Select FPGA14 or FPGA13 as source
- 8,400-pin MEG-Array connectors (FCI) for daughter card (DC) expansion
- 190 single-ended on DC0,1,2,7
- 47 LVDS pairs (FPGA -> DC), 48 LVDS pairs (DC -> FPGA) on DC[6:3]
- Can be used as 190 single ended signals
- 600Mhz (1.2Gb/s)
- Pin multiplexing to/from daughter cards using I/O shift registers (up to 10x)
- Supplied power rails (fused):
- +12V (24W Max)
- +5V (10W Max)
- +3.3V (10W Max)
- Fast and painless FPGA configuration
- CompactFlash and/or USB
- Integrated sanity checks on configuration files
- Accelerated configuration readback
- Custom base plate (standard) and optional 19" rackmount chassis
- Provides protection from those drooling SW engineers
- 4, RS232 ports for embedded uP debug
- Accessible from all FPGAs
- Full support for embedded logic analyzers via JTAG interface
- SignalTap and other third party tools
- Convert a pair of MEG-Array expansion connectors to interconnect with the DNMEG_Intercon
- MEG-Array Daughtercard Expandsion
- Enough status LEDs to adequately illuminate a Bon Jovi concert
- Product Datasheet [PDF - 1.5MB]
- Block Diagram (LVDS) [PDF - 1.7MB]
- Block Diagram (Single-ended) [PDF - 1.6MB]