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DVI Daughtercard

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  • DVI Channels:


    • 2 Input channels (Dual-Link)


      • 24 bit/pixel, 16M colors

      • SXGA and up to SXGA (and beyond)


    • 2 Output channels (Dual-Link)


      • Resolutions up to QUXGA


    • Sync Detect feature for Plug & Display "Hot Plugging"

    • 5m cabling distance with twisted pair

    • DVI 1.0 complaint


  • Xilinx Virtex-4 FPGA


    • FX60 or FX100 in -10, -11, or -12 speed grades

    • 1152 BGA package

    • 100% FPGA resources available for user application


  • 400-pin connector (DNMEG_DVI-400) for high-speed mating to:


    • DN8000kPSX

    • DN7000k10PCI

    • DN9000k10, DN9000k10PCI, DN9000k10PCIe-4GL, DN9200k10PCI, DN9002k10PCI

    • DN9000k10PCIe-8T, DN9002k10PCIe-8T

    • Stand-alone operation with off-the-shelf ATX power supply


  • 200-pin connector (DNMEG_DVI-200) for high-speed mating to:


    • DN8000k10PCI

    • Stand-alone operation with off-the-shelf ATX power supply


  • DDR2 SODIMM:


    • 64-bit data width, 200MHz operation

    • PC2-3200/PC2-4200

    • Addressing and power to support 4GB

    • Verilog/VHDL reference design provided (no charge)

    • DDR2 SODIMM data transfer rate: 25.6Gb/s

    • Alternate pin-compatible SODIMM痴


      • QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor, DDR1, DDR3



  • RS232 port for PowerPC processor visibility (TX/RX)

  • Logic Analyzer compatible Mictor connector

  • Full support for embedded debug (via JTAG)


    • ChipScope, ChipScope PRO and other third party tools


  • Two PowerPC 405 Cores (in FPGA)


    • Auxiliary Processor Unit Interface (User Coprocessor)

    • Embedded 450 MHz Harvard Architecture

    • Hardware Multiply/Divide Unit

    • Thirty-Two 32-bit Gen. Purpose Registers

    • 16 KB 2-Way Set-Assoc. Instruction Cache

    • 16 KB 2-Way Set-Associative Data Cache

    • Memory Management Unit (MMU)

    • Timer Facilities


  • Gigabit serial I/O interfaces:


    • SFP (Small form factor) module (DNMEG_DVI-400 only)

    • SMA connectors for off-board cabling to 8 channels of rocketI/O (5 with DNMEG_DVI-400)


      • 6.5Gb/s with appropriate FPGA speed grade

      • Samtec cables for off-board cabling of 10 channels of rocketI/O


    • Clocking options available for standard communications data rates for RocketIO:


      • 1x, 2x, 4x Fibre Channel

      • 10G Fibre Channel

      • XAUI

      • Serial Rapid IO Type 1,2,3

      • Serial ATA Type 1,2

      • PCI Express

      • Infiniband

      • OIF SxI-5

      • OIF SFI-4.2

      • OC-48

      • 1000 BaseX

      • OC-12

      • Aurora


    • Ability to use embedded Ethernet MAC (FX) with SFP and SMA connectors.

    • 8b/10b or 64b/66b encoding for all RocketIO channels

    • Up to 10 channels via 2 Samtec QSE-DP connectors


  • 3 separate programmable clock synthesizers and 2 fixed oscillators

  • 10 user-controllable LED's Enough to illumination to tan a large ostrich


  • Block Diagram - [PDF - 1.53MB]

  • Product Brief - [LO - 657KB]

  • DVI Specification - [PDF - 1.33MB]

  • 200-pin Header Connection Summary [XLS - 2.7MB]


  • MEG Array Daughter Card Interface Description [PDF - 660KB]

  • Daughter Card Compatibility Guide [PDF - 63KB]


  • Downloads Page

  • SODIMM Connection Summary [XLS - 77KB]

 



Digital Video Interface Daughtercard

Virtex-4 Based



Overview


The DNMEG_DVI-200 and DNMEG_DVI-400 provide dual-link input and dual-link output Digital Video Interface (DVI) functionality.



2 Receive Channels of Dual-Link DVI


The receiver channels utilize the Silicon Image SiI163B PanelLink Receiver chip. The SiL163B is DVI1.0
compliant. All 48-bits of the digital interface, along with associated control, is connected to a Xilinx Virtex-4 FX
FPGA.

2 Transmit Channels of Dual-Link DVI

The transmit channels utilize the Silicon Image SiL178 (for the 200-pin version) or the SiL1178 (for the 400-pin version). The SiL1178 supports single link resolutions of VGA to UXGA resolution (25 -165Mpps) and dual link resolutions of up to QUXGA (330Mpps). Configuration of the SiI1178 is accomplish using an I2C bus connected to the FPGA, and controlled, usually, by one of the PowerPC's resident in the FX FPGA. Example verilog/VHDL, and 'C' is provided.

Xilinx Virtex-4 FX FPGA

The DNMEG_DVI achieves high gate density and allows for fast target clock frequencies by utilizing an FPGA from Xilinx's Virtex-4 FX family for logic and memory. A high I/O-count, 1152-pin, flip-chip BGA is employed, providing for abundant flip-flops and logic. XST synthesis scripts are provided, so no third party tools are needed ・ just Foundation from Xilinx.

DDR2 Memory and other features

A DDR2 SODIMM socket connects to the FPGA and works with off-the shelf memory modules. At present, 2GB SODIMM's are readily available and the price is reasonable. We have alternative SODIMM's if you want to prototype other forms of memory. The list includes RLDRAM, FLASH, SSRAM, QDR SSRAM, SDRAM, DDR1, and others. If you want to debug using an old-fashioned logic analyzer, we have an SODIMM that has mictors. An RS232 port allows processor-based visibility, but requires UART logic in the FPGA. Working examples are shipped with the board. A JTAG port allows for ChipScope debug. Other third party tools debug use JTAG.

RocketI/O

8 (5 for DNMEG_DVI-400) channels of RocketI/O are connected to SMA's, allowing for very high-speed interconnection rates. On the DNMEG_DVI-400, an SFP socket has been added, enabling a wide selection of standard serial interfaces.

Hosted or Stand-Alone

The DNMEG_DVI-200 is intended to daughter to our ASIC emulation products that use the FCI-Berg 200-pin connector. The DNMEG_DVI-400 is intended to daughter to our ASIC emulation products that use the FCI MEG Array 400-pin connector. Either board can be used stand-alone with an off-the-shelf ATX power supply.

Debug LED's

Ten LED's are available for debug and any other application the user sees fit. We use the LED痴 here in La Jolla to tan Burt, a large male African ostrich (Struthio camelus).

DNDVI_DC200




DNDVI_DC400