- 1から2個のFF1760パッケージのXilinx Virtex-5によるPCI-ホストのロジック・プロトタイピング・システム
- XC5VLX110-1,-2,-3
- XC5VLX220-1,-2
- XC5VLX330-1,-2
- ユーザ・アプリケーションのために100%のFPGAリソースが利用可能
- LX330 2個の場合はほぼ4百万ASICゲート
- FPGA間の配線はシングル・エンドあるいはLVDS
- チップ間は450MHz DDR LVDS (900Mb/s)、あるいは225MHzシングルエンド
- ISERDES/OSERDESのリファレンスデザインを提供
- LVDS 1ペア当たり10のピン・マルチプレクシング可能
- 論理の分割を大幅に単純化
- LVDS用にソース同期クロック
- メインバス（MB）は信号数40
- シングル・エンド
- FPGAおよびConfig FPGAの両方に接続
- 自動分割のために Auspy用モデルを提供
- BのFPGAはコネクタ接続DDR2 SODIMM (200 MHz)
- 64ビットのデータ幅、200MHzの動作
- PC2-3200/PC2-4200
- 各ソケットで4GBまでのアドレスと電源をサポート
- DDR2のVerilog/VHDLリファレンス・デザインを提供（無償）
- DDR2 SODIMM のデータ転送レートは 25.6GB/秒
- ピン互換ドータカードも提供可能（当社までお問い合わせください）
- QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor, DDR1
- Seven board-level global clock networks
- 3本のボードレベル・グローバル・クロック・ネットワーク(GCLK0, GCLK1, GCLK2）
- 個々のネットワークは独立してプログラム可能
- CompactFlash あるいは USB でユーザがコンフィギュレーション
- グローバル・クロック・ネットワークはディファレンシャル・バランス配線
- 個々のグローバル・クロック・ネットワークはシングルステップのクロックが入力可能
- ドータ・カードによって柔軟にカスタマイズ
- 400ピンのMeg-Arrayコネクタ x2 (FCI)
- LX330では93のLVDSペア+クロック（あるいは186のシングルエンド）
- LVDSではすべての信号で450MHZ以上
- 信号電圧はドータカードによって設定
- リセット、カードの存在を検出
- パワー・レイル (fused) の供給
- +12V (最大24W)
- +5V (最大10W)
- +3.3V (最大10W)
- ISERDES/OSERDESおよびLVDS (最大10x)を利用してドータ・カードとの間でピン・マルチプレクシングが可能
- FPGAのコンフィギュレーションは高速かつ簡単
- CompactFlash, PCI, あるいは USB, JTAG
- コンフィギュレーション・ファイルの正常性チェック
- JTAGインタフェースを通じてエンベデッド・ロジック・アナライザはフル・サポート
- 高速な configuration readback
- 北太平洋の4匹のタコを驚かすほどの十分なLED
- DN9200K10PCI Block Diagram[PDF - 833KB]
- DN9200K10PCI Product Brief[HI - 4.63MB | LO - 400KB]
- DN9200K10PCI Manual[PDF - 7.0MB]
- DN9200K10PCI Errata[PDF - 46KB]
- MEG Array Daughter Card Interface Description [PDF - 660KB]
- Daughter Card Compatibility Guide [PDF - 63KB]
- QL5064_INTERFACE Module Description and Usage [PDF - 357KB]
- Dini Group Mainbus Specification [PDF - 167KB]
- Dini Group USB Specification [ZIP - 180KB]
- Downloads Page
DN9200K10PCI
Xilinx Virtex-5 Based ASIC Prototyping Engine
Overview
The DN9200k10PCI is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN9200k10PCI is hosted on a 32/64-bit, 33/66MHz PCI bus, or can be used stand-alone and configured via USB or CompactFlash. A single DN9200k10PCI configured with two Xilinx Virtex-5, XC5VLX330's can emulate up to 4 million gates of logic as measured by LSI (or at least how LSI used to measure ASIC gates when they manufactured ASIC's). This number does not include the embedded memories and multipliers resident in each FPGA, all of which are 100% available to user application. The DN9200k10PCI achieves high gate density and allows for fast target clock frequencies by utilizing FPGA's from Xilinx's Virtex-5 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGA's can be stuffed.
Virtex-5 FPGAs from Xilinx
The DN9200k10PCI uses high I/O-count, 1760-pin, flip-chip BGA packages. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGA's. All pins of all banks of both FPGA are utilized. FPGA to FPGA busses are routed and tested LVDS, run at 400MHz+ but can be used single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A 36-pin main bus (MB) is connected to both FPGA's including the Spartan configuration FPGA, allowing for data movement via USB.
Daughter cards
Three 400-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from these cards are routed differentially and can run at the limit of the FPGA. Clocks, resets, and presence detection, along with abundant power are included in each connector. Two of these connectors are on the bottom of the PWB and are fully populated with signals using any possible stuffing option (LX110, LX220, or LX330). The third is on the top and requires FPGA B be stuffed with an LX330.
Memory
Two DDR2 SODIMM sockets are stuffed - one for each FPGA. The sockets are tested to 250MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMM's (PC2-4200) work nicely and we can provide these for a small charge. We have developed alternative SODIMM's that can be stuffed into these positions. Consult the factory for more details, but the list includes Flash, SSRAM, QDR SSRAM, mictors, RLDRAM, DDR1, and others.
Easy Configuration Via CompactFlash or USB
The configuration bit files for the FPGA's are copied onto a CompactFlash card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. FPGA configuration occurs over the highest-speed parallel SelectMap interface. Multiple LED's provide instant status and operational feedback.
Other Cool Stuff
Many FPGA-controlled LED's provide for visual status. Although no laboratory testing was performed, statistical animal models are showing this to be enough illumination to completely cure Seasonal Affective Disorder (SAD) in a Yak. Three Mictor connectors enable observation via logic analyzers from Tektronix and HP.
As always, reference material such as DDR SDRAM controller included (in Verilog, VHDL) at no additional cost.
Specs of FPGAs Avaliable on the DN9200K10
