アプリスター

• PCI-hosted logic prototyping system with 2-6 Xilinx Virtex-5 FPGAs
  
  
  
  • XC5VLX110, XC5VLX220, or XC5VLX330 (FF1760)
    
  
  
• 100% FPGA resources available for user application
  
• Nearly 12M ASIC gates (LSI measure) with 6 LX330s
  
• FPGA to FPGA interconnect is single-ended or LVDS
  
  
  
  • 400Mhz LVDS (800Mb/s) chip to chip
    
  • Reference designs for integrated I/O pad ISERDES/OSERDES
    
    
    
    • 10x pin multiplexing per LVDS pair
      
    
    
  • Greatly simplified logic partitioning
    
  • Source synchronous clocking for LVDS
    
  
  
• Main Bus (MB) connects all LX FPGAs (169 signals)
  
  
  
  • Single-ended
    
  
  
  
• 6 separate DDR2 SODIMMs (250MHz)
  
  
  
  • 1 SODIMM each for FPGAs A,B,F,D
    
  • 2 SODIMMs for FPGAs C
    
  • 64-bit data width, 250MHz operation
    
  • PC2-3200/PC2-4200
    
  • Addressing/power to support 4GB in each socket
    
  • DDR2 Verilog/VHDL reference design provided (no charge)
    
  • DDR2 SODIMM data transfer rate: 26Gb/s
    
  • Alternate pin compatible memory cards available (consult factory for availability):
    
    
    
    • Click here to see the compatibility chart for DNSODM products
    
    
    • QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor
      
    
    
  
  
• 7 board-level global clock networks (GCLK0, GCLK1, GCLK2)
  
  
  
  • Three separate programmable synthesizers
    
    
    
    • User configurable via CompactFlash or USB
      
    
    
  • Global clocks networks distributed differentially and balanced
    
  • Single-step clocking available on two global clock networks
    
  
  
• 3 external differential clock inputs
  
• Flexible customization via daughter cards
  
  
  
  • Three 400-pin Meg-Array connectors (FCI)
    
    
    
    • FPGAs D,E,F
      
    • 93 LVDS pairs + clocks (or 186 single-ended)
      
    
    
  • 400MHz on all signals with LVDS
    
  • Signal voltage set by daughter card
    
  • Reset
    
  • Supplied power rails (fused):
    
    
    
    • +12v (24W max)
      
    • +5V (10W max)
      
    • +3.3V (10W max)
      
    
    
  • Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)
    
  
  
• Fast and Painless FPGA configuration
  
  
  
  • Compact Flash, PCI, JTAG, and/or USB
    
  • Integrated sanity checks on configuration files
    
  • Accelerated configuration readback
    
  
  
• RS232 port for embedded uP debug
  
  
  
  • Accessible from all FPGAs
    
  
  
• Full support for embedded logic analyzers via JTAG interface
  
  
• Enough status LEDs to blind a large sloth
  
• Convert MEG Array expansion connectors to interconnect with the DNMEG_Intercon. Add 186 single-ended OR 93 pairs LVDS:




• (FPGA D to E) OR (FPGA E to F)




• Now 100% RoHS!

• DN9000K10PCI Press Release - [PDF - 104KB] [DOC - 186KB]


• DN9000K10PCI Product Brief - PDF[HI - 12.1MB|LO - 781KB]


• DN9000K10PCI Block Diagram - PDF[LX330 - 315KB|LX220 - 310KB]


• DN9000K10PCI User Manual - [PDF - 6.91MB]


• DN9000K10PCI FPGA Selection - [XLS - 9KB] [PDF - 42KB]


• DN9000K10PCI Dimensions - [PDF - 48KB]


• DN9000K10PCI Errata - [PDF - 46KB]





• MEG Array Daughter Card Interface Description [PDF - 660KB]


• Daughter Card Compatibility Guide [PDF - 63KB]


• QL5064_INTERFACE Module Description and Usage [PDF - 357KB]


• Dini Group Mainbus Specification [PDF - 167KB]


• Dini Group USB Specification [ZIP - 180KB]


• Downloads Page

DN9000K10PCI
Xilinx Virtex-5 Based ASIC Prototyping Engine

Overview

The DN9000k10PCI is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN9000k10PCI is hosted on a 32/64-bit, 33/66MHz PCI bus, or can be used stand-alone and configured via USB. A single DN9000k10PCI configured with 6 Xilinx Virtex-5, XC5VLX330s can emulate up to 12 million gates of logic as measured by LSI (or at least how LSI used to measure ASIC gates when they manufactured ASICs). This number does not include the embedded memories and multipliers resident in each FPGA, all of which are 100% available to user application. The DN9000k10PCI achieves high gate density and allows for fast target clock frequencies by utilizing FPGA's from Xilinx's Virtex-5 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGAs can be stuffed.

Virtex-5 FPGAs from Xilinx
The DN9000k10 uses high I/O-count, 1760-pin, flip-chip BGA packages. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGA's. All pins of all banks of each FPGA are utilized. FPGA to FPGA busses are routed and tested LVDS, run at 400MHz+ but can be used single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A 169-pin main bus (MB) is connected to all FPGAs including the Spartan configuration FPGA.

Daughter cards
Three separate 400-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from these cards are routed differentially, and can run at the limit of the FPGA: 400MHz. Clocks, resets, and presence detection, along with abundant power are included in each connector.

Memory
Six separate DDR2 SODIMM sockets are stuffed and have connections to FPGAs A, B, D, F, and C (two separate sets). Each socket is tested to 200MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMMs (PC2-3200/PC2-4200) work nicely and we can provide these for a small charge. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes Flash, SSRAM, QDR SSRAM, mictors, PC100, and PC2700.

Easy Configuration Via Compact Flash or USB
The configuration bit files for the FPGA's are copied onto a Compact Flash card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. FPGA configuration occurs over the highest-speed parallel SelectMap interface. Multiple LED's provide instant status and operational feedback.

As always, reference material such as DDR SDRAM controller included (in Verilog, VHDL) at no additional cost.

Specs of FPGAs Avaliable on the DN9000K10