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- 8-lane PCI Express (PCIe) logic prototyping system available with Xilinx Virtex-4 FPGA's.
- Stuffing options for 1,2, or 3 FPGA's from the following list:
- -2 from 'LX' family FPGA A and FPGA B (FF1513):
- -4VLX100-10,-11,-12
- -4VLX160-10,-11,-12
- -4VLX200-10,-11
- -1 from 'FX' family FPGA C (FF1152):
- 4VFX40-10,-11,-12
- 4VFX60-10,-11,-12
- 4VFX100-10,-11,-12
- 100% FPGA resources available for user application
- User must supply PCIe controller
- Nearly 3.7M ASIC gates (LSI measure)
- All FPGA to FPGA interconnect LVDS differential
- 350 Mhz differential chip to chip
- Reference designs for integrated ISERDES/OSERDES
- 10x pin multiplexing per LVDS pair
- FPGA A to FPGA B interconnect: >1800 signals
- Greatly simplified logic partitioning
- 5 separate programmable clock synthesizers (ICS8442)
- 3 Global clocks (ACLK, BCLK, DCLK)
- 2 for rocketI/O specific functions
- User configurable via SmartMedia, PCIe, or USB
- Genesys Logic GL9714 PCI Express PIPE Phys
- Xilinx FX rocketI/O's not used for PCIe function
- Advanced FPGA configuration via USB2.0 or SmartMedia
- Partial reconfiguration support on all FPGAs
- 2 separate DDR2 SODIMMs (200MHz)
- Connected to: FPGA B (LX), FPGA C (FX)
- 64-bit data width, 200MHz operation
- PC2-3200/PC2-4200
- Addressing and power to support 4GB in each socket
- Verilog/VHDL reference design provided (no charge)
- DDR2 SODIMM data transfer rate: 25.6Gb/s
- Alternate pin compatible memory cards available:
- Click here to see the compatibility chart for DNSODM products
- QDR SSRAM, FLASH, SSRAM, Mictor, RLDRAM
- Gigabit serial I/O interfaces (via FX FPGA):
- 2 -- 10G, Small form factor XFP (or SFP) modules
- SMA connectors for off-board cabling to 4 channels of rocketI/O 10Gb/s
- Samtec cables for off-board cabling of 10 channels of rocketI/O
- Clocking options available for standard communications data rates for RocketIO:
- 1x, 2x, 4x Fibre Channel
10G Fibre Channel, XAUI, Serial Rapid IO Type 1,2,3, Serial ATA Type 1,2,
PCI Express, Infiniband, OIF SxI-5, OIF SFI-4.2, OC-48, 1000 BaseX,
OC-12, Aurora - Ability to use embedded Ethernet MAC (FX) with SFP/XFP/SMA connectors.
- 8b/10b or 64b/66b encoding for all RocketIO channels
- Two PowerPC 405 Cores in FPGA C (FX)
- RS232 ports for PowerPC/uP observation/debug
- Multiplexed via SpartanII Configuration FPGA
- Enough Status LED's to blind a medium-sized ferret
- Standalone operation with off-the-shelf ATX power supply.
- Two, 200-pin expansion connectors with 284+ connections
- Custom daughter cards
- DN3k10SD Observation Daughter Card
- DNPMC104 Embedded Systems Board Carrier
- Single-ended or LVDS, +2.5/3.3V tolerant
- We recommend using the Daughter Card Extender when using 200-pin daughtercards.
- Full support for embedded logic analyzers via JTAG interface
- Now 100% RoHS! Rev. 2 ONLY
- Block Diagram [PDF - 225KB]
- Product Brief [Hi PDF - 5MB | Lo PDF - 362KB]
- GL9714 Datasheet [PDF - 374KB]
- Manual [PDF - 2.17MB] [DOC - 34.1MB]
- Errata [PDF - 72KB]
- MEG Array Daughter Card Interface Description [PDF - 660KB]
- Daughter Card Compatibility Guide [PDF - 63KB]
- QL5064_INTERFACE Module Description and Usage [PDF - 357KB]
- Dini Group Mainbus Specification [PDF - 167KB]
- Dini Group USB Specification [ZIP - 180KB]
- Downloads Page
- SODIMM Connection Summary [XLS - 77KB]
DN8000K10PCIe-8
Virtex4 Based
ASIC Prototyping Engine
The DN8000K10PCIe-8 is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and
memory designs for a fraction of the cost of existing solutions. The DN8000K10PCIe-8 is hosted in an 8-lane PCI Express slot
or can be used stand-alone. The user must supply the PCIe-8 controller in FPGA A. Two Genesys Logic GL9714's are used for the
PCI Express Phy function, freeing up all FX rocketI/O's for other applications. A single DN8000K10PCIe-8 configured with 2
4VLX200's and a single 4VFX100 can emulate up to 3.7 million gates of logic as measured by LSI. And this number does not include
the embedded memories and multipliers/ALU's resident in each FPGA. The DN8000K10PCIe-8 achieves high gate density and allows
for fast target clock frequencies by utilizing FPGA's from Xilinx's Virtex-4 LX/FX families for logic and memory. High I/O-count,
1513-pin, flip-chip BGA packages (for LX) and 1152-pin BGA's (for FX) are employed, providing for abundant, fixed interconnect
between the FPGA's. All FPGA interconnect is single-ended or differential, with differential clocked at 350MHz+. In addition,
the OSERDES/ISERDES functionality is thoroughly tested and characterized, allowing for 10x pin multiplying on differential
pairs between FPGA's and dramatically easing the partitioning problem. Two DDR2 SDRAM SODIMM sockets are provided, allowing
for up to 8GB of DDR2 memory. Each socket is tested at 200MHz, and reference designs are provided. Alternate pin-compatible
SODIMMs are available that contain FLASH, RLDRAM, SSRAM, QDR SSRAM, or Mictor connectors. A total of 304+ test pins are
provided on the top of the PWB via two 200-pin expansion headers. These expansion headers can also be used for logic analyzer-based
debugging or for pattern generator stimulus. The DNPMC104 card can be mounted to any of these connectors, enabling an
interface to A/D's, D/A's, and a host of other embedded system peripherals. Also, custom daughter cards can be mounted to these
connectors as a means to interface the DN8000K10PCIe-8 to application-specific circuits. Two XFP modules can be used to support
OC-192/STM-64, 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, and G.709 data streams and can be connected to routers, switches
and network cards. Reference material such as DDR2 SDRAM controllers and PowerPC code is included (in Verilog, VHDL, C) at no
additional cost.
Specs of FPGAs Avaliable on the DN8000K10PCIe-1
