アプリスター

• PCI Express (PCIe) PWB (1-lane)
  • Up to 6 VirtexII-Pro or ProX FPGAs in FF1704
    • 2vp70-5,-6,-7 or 2vp100-5,-6 or 2vpx70-5,-6,-7
  • Flexible, abundant, and configurable embedded memory in FPGA's
    • 444 18-kbit memory blocks per FPGA (2vp100)
    • Up to 1.378 Kbytes Distributed SelectRAM per FPGA (2vp100)
    • 100% of FPGA resources available for user applications
  • 2 -- 200-pin high-speed expansion connectors for awesome signal integrity
    • Custom daughter cards
    • Standard Daughter cards:
      • Camera Link/LVDS
      • DNPMC104
      • DN3k10SD/ DN3k10SD_mictor
  • 10 DDR SDRAM's (with 2vp100's)
    • standard: 32M x 16
    • Options for 64M x 16 DDR devices
    • 2 DDRs connected to FPGAs B, C, D, E, and F
• 8 off-board, RocketI/O-based high-speed serial ports
  • SMB Connectors (2 MGTs each)
  • 2 ports each connected to FPGAs A, B, E, F
  • 3.125 GB/S (with -6, or -7 speed grade FPGA)
• 20A on-board switching regulator for both +2.5V and +1.5V
  • Standalone operation with an off-the-shelf ATX power supply
• Two PowerPC 405 Cores per FPGA (12 total with six FPGA's)
  • Embedded 300+ MHz Harvard Architecture
  • Hardware Multiply/Divide Unit
  • Thirty-Two 32-bit General Purpose Registers
  • 16 KB 2-Way Set-Assoc. Instruction Cache
  • 16 KB 2-Way Set-Associative Data Cache
  • Memory Management Unit (MMU)
  • Timer Facilities
• Status LED's provide instant status and operational feedback
• Four RS232 ports for PowerPC observation/debug
  • Four full duplex (RX/TX)
  • All four ports multiplexed via SpartanII Configuration FPGA
• Fast/Easy FPGA configuration via standard SmartMedia FLASH card
  • Microprocessor controlled (CY7C68013)
  • Separate RS232 port for configuration/operational status and control
  • Fastest possible configuration using SelectMap
  • Sanity checking programs for bit files simplify the configuration process
• 2 low skew clocks distributed to all FPGA's and headers:
  • 2 user-selectable socketed oscillators
  • PCIe Clock
  • 2 CY7B993/4 RoboClockII PLL's for the best clock distribution
• Robust observation/debug with 480+ connections for logic analyzer observability and pattern generator stimulus.
• Boatloads of reference stuff included (FREE)
• DDR SDRAM controller (Verilog/VHDL)
• PowerPC 'Hello World'
  • UART's
  • USB utilities
  • Board test(s)
  • Windows XP, ME, 2000, 98, NT, LINUX, Solaris
• Full support for embedded logic analyzers via JTAG interface
  • ChipScope, ChipScope PRO
  • Identify? from Synplicity

• Product Brief - PDF[HI - 4.86MB| LO - 295KB]
• Block Diagram [PDF - 159KB]
• Virtex II Pro Errata [PDF - 27KB]

DN6000k10PCIe-1
VirtexII™-Pro Based
ASIC Prototyping Engine
PCI Express (PCIe)
(1-lane)

The DN6000K10PCIe is a complete logic emulation system that enables ASIC or IP designers to prototype logic, memory, and embedded systems designs for a fraction of the cost of other solutions. The DN6000K10SE is hosted in a 1-lane PCI Express slot (PCIe) and can be used standalone. This product supports up to 6 FPGAs and each position can be populated by either a 2vp70, 2vp100, or 2vpx70. A DN6000K10PCIe stuffed with 6 2vp100s can emulate up to 4.5+ million gates of logic as measured by LSI. In addition, each 2vp100 VirtexII Pro FPGA contains two 300MHz+ 405 PowerPC microprocessors, 444 18x18 multipliers, and 7.992 Mbytes of block RAM memory. Eight serial RocketI/O ports are provided on the corners of the circuit board and can support a variety of serial communication protocols at speeds up to 3.125 GB/s (with -6, -7 speed grade), with 10 GB/s to follow with the 'X' family.
The DN6000K10PCIe is designed for performance. All external memories run at a frequency of at least 133MHz and the FPGA internal speed is limited only by the logic within. The FPGAs are high I/O count, 1704-pin BGA packages, allowing for maximum chip to chip interconnect. Two 200-pin expansion connectors provide for expansion capability.

Easy Configuration Via SmartMedia

The configuration bit file for the FPGA is copied onto a 32/64/128-megabyte SmartMedia FLASH card (provided) and an on-board microprocessor controls the FPGA configuration process. An RS232 port provides detailed information regarding the configuration process, completely bypassing time-consuming debugging of the configuration process. FPGA configuration occurs at close to the fastest possible parallel frequency -- 48MHz. Eight LED's provide instant status and operational feedback. Two of these LED's are connected to the CPLD and can be user-configured.