We provides the following tools:
-
ASIM: Generating Sophisticated Scenarios at the Architecture Level
-
Support standard networking and multimedia protocols
-
By Any designer or verification engineer
-
API for non-standard protocols
-
-
AMB: Advanced Assertions with your ASIC C-Model
-
All the Interfaces, including memory contents, are monitored
-
Debugging without looking at waveform
-
-
PRTG: Creating Sophisticated Test Cases Automatically
-
By any designer or verification engineer
-
Build-in advanced constraint solver
-
Constraint randomization technology without programming
-
-
DIM: Most Automated Verification IP for any ASIC Interfaces
-
PCI Express, Ethernet, USB
-
Advanced error injection
-
Reusable for ESL/RTL/Emulation/Bring-up with same test cases
-
Customization for non-standard and not-yet-supported interfaces
-
-
ADG: Multi-Threaded ASIC Configuration
-
Reusable ASIC Driver generated automatically from Register Definition File
-
Linux Kernel-like C/C++ multi-threaded programming paradigm
-
C/C++ Libraries support reusable verification methodology
-
Using Dynamic Simulation Control (DSC) for scripting without performance penalty
-
-
SDL: Unified System Description for Everything in the Verification Environment
-
Reusable for the current ASIC at different levels, such as ESL/RTL/Emulation/Bring-up
-
Reusable for the next generation ASIC
-
Productivity Improvement: One verification engineer supports 2 designers
-
-
Complied Test Suites for Standard Interfaces
-
Such as PCI Express, Ethernet, USB, etc.
-
All your team need to do is to complete the followings:
-
ASIC C/C++ Model for Assertions
-
AMB provides the co-simulation interface to your ASIC
-
-
A Full-Coverage Regression Suite
-
PRTG automatically generate test cases with guidance from your team
-
-
24x7 Effective Random Regression
-
Based on a set of SDL objects that has full coverage on your ASIC
-
Taping out your ASIC after bug-free for two weeks
-
Draco gives you Repeatable First-Silicon Success on schedule while lowering your budget.
