Overview
PCIE-VR is a software implementation of the PCI Express (PCIE) standards. It is designed to be a Verification IP and an architecture model to facilitate ASIC designs with a PCIE interface. A set of verification automation tools and a compliance suite are added to increase the productivity.
PCIE-VR fully models and monitors PCI Express functionality, timing, and protocols at both the cycle-accurate and transaction levels. It also generates realistic sophisticated concurrent-test scenarios automatically in all the three layers. For the transaction layer verification, PCIE-VR features a multi-threaded traffic generator that greatly simplifies the verification of concurrent access to the designs. For the data link and physical layers, PCIE-VR features powerful randomized state machine exercisers that exhaustively verify the flow control protocol, DLCMSM, and LTSSM.
As a VIP, PCIE-VR verifies all PCIE ASIC designs, such as root complex, switches, end points, and bridges at both Register-Transfer Level (RTL) and Electronic System Level (ESL).
As an architecture model, PCIE-VR is a Transaction-Level Model (TLM) that enables architecture designs of PCIE devices. PCIE-VR TLM is up to 300X faster than a cycle-accurate model. Due to the high performance, PCIE-VR TLM is also ideal for test case validation and software development.
PCIE-VR contains a PCI Express compliance suite that has hundreds of directed test cases and is capable of generating unlimited number of sophisticated random test cases. A functional coverage grader that is based on the PCI_SIG compliance check list provides the capability to go through the compliance check list before the tape out.
Features
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Supports PCIE standard version 1.0a, 1.1, and Gen2.
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Supports all standard interfaces, serial, PIPE, 8/10b, and parallel.
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Comprehensive Plug&Play PCIE compliance suite and functional coverage grading. (click here for example)
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Built-in PCIE packet/state/protocol monitor.
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Realistic high-performance multi-threaded programming environment. (click here for example)
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Sophisticated test scenario generations at all three layers automatically. (click here for example)
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Powerful error injections with ease-of-use high-level control. ( click here for example)
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Automatic exhaustive test of ALL DUT registers and memories, not just PCIE configuration registers.
