Fastest and Accurate PCIE Models
PCIE-VR has both cycle-accurate model (CAM) and transaction-level model (TLM).
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Three kinds of APIs, i.e., C, Verilog, and DSC script for ease of programming.
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Cycle-accurate Model (CAM) with PIPE, PCS, and serial interfaces.
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Fastest Transaction Level Model for architecture design, test case development, and software-hardware co-verification.
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Supports for multiple PCIE device instances in one PCIE0-VR instance.
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Supports for any verification language and test bench.
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Supports for third-party architecture design tools.
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Fully configurable at run time ?Ebetter than compilation options.
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Supports for simulation speed-up, such as zero-time configuration, backdoor access, state bypass, etc.
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A rich set of User-Defined Functions for customization, such as performance analysis.
Realistic traffic: Multiple PCIE devices are modeled in one instance
